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參數(shù)資料
| 型號： | TMS320AV220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video CD MPEG Decoder(視頻CD MPEG編碼器) |
| 中文描述： | 視頻CD MPEG解碼器（視頻光盤的MPEG編碼器） |
| 文件頁數(shù)： | 23/31頁 |
| 文件大小： | 612K |
| 代理商： | TMS320AV220 |
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TMS320AV220
VIDEO CD MPEG DECODER
SCSS016A – JUNE 1994 – REVISED JANUARY 1996
23
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements and switching characteristics over recommended ranges of supply voltage
and operating free-air temperature range (unless otherwise noted) (continued)
Sony CD-ROM interface timing, CDSEL = 0 (see Figure 11)
MIN
MAX
UNIT
t1
t2
t3
t4
t5
t6
CDEN high after CDREAD output high
120
ns
CDEN low
55
ns
CDATA before CDEN high
50
ns
CDATA hold time after CDEN high
20
ns
CDERROR before CDEN high
50
ns
CDERROR after CDEN high
20
ns
Sanyo CD-ROM interface timing, CDSEL = 1 (see Figure 12)
MIN
MAX
UNIT
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
CDEN low to CDREAD output low
0
ns
CDREAD output low time
310
ns
CDREAD output high time
CDWAIT
↓
after CDREAD output low
CDREAD output high after CDWAIT high
50
ns
80
ns
50
ns
CDWAIT low time
625
ns
CDATA before CDREAD output high
50
ns
CDATA hold after CDREAD output high
0
ns
CDATA before CDWAIT high
0
ns
CDERROR high before CDREAD output high
50
ns
CDERROR hold after CDREAD output high
0
ns
video bus timing (see Note 2 and Figure 15)
MIN
MAX
UNIT
fclock
tw3
tsu8
th2
tpd3
ten
tdis
NOTES:
VCLK frequency
14.9
MHz
VCLK high or low
20
ns
HSYNC before VCLK high
10
ns
HSYNC after VCLK high
0
ns
VCLK high to PD23–PD0
20
ns
VOE low to PD23–PD0
20
ns
VOE high to PD23–PD0 (see Notes 3 and 4)
20
ns
2. Inputs switch between 0 V and 3.5 V at 1 V/ns. Measurements are made at 1.5 V. Output load capacitance = 50 pF.
3. Not 100% tested, specified by design and characterization
4. Time at which output achieves the high-impedance condition; not referenced to an output-voltage level
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| TMS320AV220PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG |
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