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參數(shù)資料
| 型號： | TMS320AV220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video CD MPEG Decoder(視頻CD MPEG編碼器) |
| 中文描述： | 視頻CD MPEG解碼器（視頻光盤的MPEG編碼器） |
| 文件頁數(shù)： | 12/31頁 |
| 文件大?。?/td> | 612K |
| 代理商： | TMS320AV220 |
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TMS320AV220
VIDEO CD MPEG DECODER
SCSS016A – JUNE 1994 – REVISED JANUARY 1996
12
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
FAST, fast-forward/fast-reverse mode (2421h) (continued)
When this register is set to 1, the device clears the input buffers, mutes the decoded audio output, and
decodes/displays only I-frames. The user data associated with each I-frame is placed in the USERDATA
registers. The user data normally contains pointers to the next/previous I-frame on the CD. An interrupt is
generated when an I-frame is found and also when the I-frame is decoded (if enabled). This allows the host to
skip on the CD to the sector containing the next I-frame. The user must not set the FAST and STILL_MODE
registers to 1 at the same time.
INTERRUPT, interrupt-request register, 7:0 (2425h)
The interrupt register shows which interrupt caused the interrupt request. This is a read-only register; the
interrupts are cleared when the host reads this register.
BIT NO.
FUNCTION
7
DMA request
6
Time-out error, a reset is required
5
I-frame decoded, still or fast mode only
4
I-frame found, still or fast mode only
3
User data found, still or fast mode only
2
DRAM full, streaming data mode only
1
MPEG data error
0
Bit-stream buffer underflow
INTR_EN, interrupt-enable register, 7:0 (2426h)
The INTR_EN register enables any interrupts that are needed by the host. A 1 in any bit position enables the
corresponding interrupt in the INTERRUPT register. A 0 masks the interrupt. After reset, no interrupts are
enabled.
RESET, reset the decoder (2424h)
0 = Normal operation
1 = Resets the video and audio. Clears all buffers, resets the video-decoder core, downloads microcode, and
initializes registers. This bit is cleared by the ’AV220 at the completion of the reset cycle. Writing a 1 to this
register is equivalent to asserting RESET; however, RESET must be asserted to initialize the device on
power up.
The host cannot read or write registers or memory until the internal reset sequence is completed, requiring up
to 25 ms. If a register access is attempted during the reset period, the chip activates the WAIT line until the reset
is completed. The CD interface does not accept data during this time. The ’AV220 activates CDREAD when the
reset sequence is completed.
STILL_MODE, still-picture-display mode, 1:0 (2422h)
Bit 0: 0 = Normal operation
1 = Frame advance. Displays the next still picture (I-frame), then clears this bit.
Bit 1: 0 = Normal operation
1 = Still-picture mode. After the bit-stream buffer is flushed, displays the first I-frame only.
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相關代理商/技術參數(shù) |
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| TMS320AV220PCM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio/Video Decoder for MPEG |
| TMS320AV410 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
| TMS320AV410PJM | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMS320AV411 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Encoder Circuit |
| TMS320AV411PJM | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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