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SYM53C876/876E Data Manual
2-3
Functional Description
PCI Functional Description
Configuration Space
Two independent sets of configuration space
registers are defined, one set for each SCSI
function. The Configuration registers are
accessible only by system BIOS during PCI
configuration cycles. Each configuration space
is a contiguous 256 x 8-bit set of addresses.
Decoding C_BE/(3-0) determines if a PCI
cycle is intended to access configuration regis-
ter space. The IDSEL bus signal is a “chip
select” that allows access to the configuration
register space only. A configuration read/write
cycle without IDSEL is ignored. The eight
lower order addresses AD (7-0) are used to
select a specific 8-bit register. Since the
SYM53C876 is a PCI multi-function device,
AD (10-8) decodes either SCSI Function A
Configuration register (AD (10-8) = 000
binary) or SCSI Function B Configuration
register (AD (10-8) = 001 binary). The host
processor uses this configuration space to ini-
tialize the SYM53C876.
At initialization time, each PCI device is
assigned a base address (in the case of the
SYM53C876, the upper 24 bits of the address
are selected) for memory accesses and I/O
accesses. On every access, the SYM53C876
compares its assigned base addresses with the
value on the Address/Data bus during the PCI
address phase. If there is a match of the upper
24 bits, the access is for the SYM53C876 and
the low order eight bits define the register to
access. A decode of C_BE/ (3-0) determines
which registers and what type of access is per-
formed.
I/O Space
PCI defines I/O space as a contiguous 32-bit
I/O address that is shared by all system
resources, including the SYM53C876. The
Base Address Zero register determines which
256-byte I/O area this device occupies.
Memory Space
PCI defines memory space as a contiguous
32-bit memory address that is shared by all
system resources, including the SYM53C876.
The Base Address One register determines
which 256-byte memory area this device
occupies. Each SCSI function uses a 4K
SCRIPT RAM memory space. The Base
Address Two register determines the 4 KB
memory area that the SCRIPT RAM occu-
pies.
PCI Bus Commands and Functions
Supported
Bus commands indicate to the target the type
of transaction the master is requesting. Bus
commands are encoded on the C_BE/(3-0)
lines during the address phase. PCI bus com-
mand encoding and types appear in Table 2-1.