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SYM53C876/876E Data Manual
Registers
SCSI Registers
wins arbitration when operating in low level
mode. When this bit is clear, the SYM53C876
SCSI function is not connected to the SCSI
bus.
Bit 2
INTF (Interrupt on the Fly)
This bit is asserted by an INTFLY instruction
during SCRIPTS execution. SCRIPTS pro-
grams do not halt when the interrupt occurs.
This bit can be used to notify a service rou-
tine, running on the main processor while the
SCRIPTS processor is still executing a
SCRIPTS program. If this bit is set, when the
ISTAT register is read it is not automatically
cleared. To clear this bit, write it to a one. The
reset operation is self-clearing.
Note: If the INTF bit is set but SIP or DIP is not
set, do not attempt to read the other chip
status registers. An interrupt-on-the-fly
interrupt must be cleared before servicing
any other interrupts indicated by SIP or
DIP.
Note: This bit must be written to one in order to
clear it after it has been set.
Bit 1
SIP (SCSI Interrupt Pending)
This status bit is set when an interrupt condi-
tion is detected in the SCSI portion of the
SYM53C876 SCSI function. The following
conditions cause a SCSI interrupt to occur:
I
A phase mismatch (initiator mode) or
SATN/ becomes active (target mode)
I
An arbitration sequence completes
I
A selection or reselection time-out occurs
I
The SYM53C876 SCSI function is
selected
I
The SYM53C876 SCSI function is
reselected
I
A SCSI gross error occurs
I
An unexpected disconnect occurs
I
A SCSI reset occurs
I
A parity error is detected
I
The handshake-to-handshake timer is
expired
I
The general purpose timer is expired.
To determine exactly which condition(s)
caused the interrupt, read the SIST0 and
SIST1 registers.
Bit 0
DIP (DMA Interrupt Pending)
This status bit is set when an interrupt condi-
tion is detected in the DMA portion of the
SYM53C876 SCSI function. The following
conditions cause a DMA interrupt to occur:
I
A PCI parity error is detected
I
A bus fault is detected
I
An abort condition is detected
I
A SCRIPTS instruction is executed in
single-step mode
I
A SCRIPTS interrupt instruction is
executed
I
An illegal instruction is detected.
To determine exactly which condition(s)
caused the interrupt, read the DSTAT regis-
ter.