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參數(shù)資料
| 型號(hào)： | SYM53C875 |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁(yè)數(shù)： | 95/243頁(yè) |
| 文件大?。?/td> | 1362K |
| 代理商： | SYM53C875 |
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SCSI Operating Registers
SYM53C875/875E Data Manual
5-9
Register 02 (82)
SCSI Control Two (SCNT L2)
Read/Write
Bit 7
SDU (SCSI Disconnect Unexpected)
T his bit is valid in initiator mode only. When
this bit is set, the SCSI core is not expecting
the SCSI bus to enter the Bus Free phase. If it
does, an unexpected disconnect error will be
generated (see the Unexpected Disconnect bit
in the SIST 0 register, bit 2). During normal
SCRIPT S mode operation, this bit is set auto-
matically whenever the SCSI core is reselected,
or successfully selects another SCSI device.
T he SDU bit should be reset with a register
write (MOVE 0X 00 T O SCNT L2) before the
SCSI core expects a disconnect to occur, nor-
mally prior to sending an Abort, Abort Tag,
Bus Device Reset, Clear Queue or Release
Recovery message, or before deasserting
SACK / after receiving a Disconnect command
or Command Complete message.
Bit 6
CHM (Chained Mode)
T his bit determines whether or not the SCSI
core is programmed for chained SCSI mode.
T his bit is automatically set by the Chained
Block Move (CHMOV) SCRIPT S instruction
and is automatically cleared by the Block Move
SCRIPT S instruction (MOVE).
Chained mode is primarily used to transfer
consecutive wide data blocks. Using chained
mode facilitates partial receive transfers and
allows correct partial send behavior. When this
bit is set and a data transfer ends on an odd
byte boundary, the SYM53C875 will store the
last byte in the SCSI Wide Residue Data Regis-
ter during a receive operation, or in the SCSI
Output Data Latch register during a send
operation. T his byte will be combined with the
first byte from the subsequent transfer so that a
wide transfer can be completed.
For more information, see the “Chained
Mode” section in Chapter 2, “Functional
Description.”
Bit 5
SLPMD (SLPAR Mode Bit)
If this bit is clear, the SLPAR register functions
like the SYM53C825. If this bit is set, the
SLPAR register reflects the high or low byte of
the SLPAR word, depending on the state of
SCNT L2 bit 4. It also allows a seed value to be
written to the SLPAR register.
Bit 4
SLPHBE N (SLPAR High Byte
E nable)
If this bit is clear, the low byte of the SLPAR
word is present in the SLPAR register. If this
bit is set, the high byte of the SLPAR word is
present in the SLPAR register.
Bit 3
WSS (Wide SCSI Send)
When read, this bit returns the value of the
Wide SCSI Send (WSS) flag. Asserting this bit
will clear the WSS flag. T his clearing function
is self-resetting.
When the WSS flag is high following a wide
SCSI send operation, the SCSI core is holding
a byte of “chain” data in the SODL register.
T his data will become the first low-order byte
sent when married with a high-order byte dur-
ing a subsequent data send transfer.
Performing a SCSI receive operation will clear
this bit. Also, performing any non-wide trans-
fer will clear this bit.
Bit 2
VUE 0 (Vendor Unique E nhance-
ments bit 0)
T his bit is a read only value indicating whether
the group code field in the SCSI instruction is
standard or vendor unique. If reset, the bit
indicates standard group codes; if set, the bit
indicates vendor unique group codes. T he
SDU
7
Default>>>
0
CHM
6
SLPMD
5
SLPHBEN
4
WSS
3
VUE0
2
VUE1
1
WSR
0
0
0
0
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
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| SYM53C875E | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O 處理器) |
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