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參數(shù)資料
| 型號(hào)： | SYM53C875 |
| 廠商： | LSI Corporation |
| 英文描述： | PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器) |
| 中文描述： | 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器） |
| 文件頁(yè)數(shù)： | 162/243頁(yè) |
| 文件大小： | 1362K |
| 代理商： | SYM53C875 |
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Instruction Set of the I/O Processor
Memory Move Instructions
6-20
SYM53C875/875E Data Manual
Bit 16
Wait For Valid Phase
If the Wait for Valid Phase bit is set, the
SYM53C875 waits for a previously unserviced
phase before comparing the SCSI phase and
data.
If the Wait for Valid Phase bit is clear, the
SYM53C875 compares the SCSI phase and
data immediately.
Bits 15-8 Data Compare Mask
T he Data Compare Mask allows a SCRIPT to
test certain bits within a data byte. During the
data compare, any mask bits that are set cause
the corresponding bit in the SFBR data byte to
be ignored. For instance, a mask of 01111111b
and data compare value of 1X X X X X X X b
allows the SCRIPT S processor to determine
whether or not the high order bit is set while
ignoring the remaining bits.
Bits 7-0 Data Compare Value
T his 8-bit field is the data to be compared
against the SCSI First Byte Received (SFBR)
register. T hese bits are used in conjunction
with the Data Compare Mask Field to test for
a particular data value.
Second Dword
Bits 31-0 Jump Address
T his 32-bit field contains the address of the
next instruction to fetch when a jump is taken.
Once the SYM53C875 has fetched the instruc-
tion from the address pointed to by these 32
bits, this address is incremented by 4, loaded
into the DSP register and becomes the current
instruction pointer.
Memory Move Instructions
For Memory Move instructions, bits 5 and 4
(SIOM and DIOM) in the DMODE register
determine whether the source or destination
addresses reside in memory or I/O space. By set-
ting these bits appropriately, data may be moved
within memory space, within I/O space, or
between the two address spaces.
T he Memory Move instruction is used to copy the
specified number of bytes from the source address
to the destination address.
Allowing the SYM53C875 to perform memory
moves frees the system processor for other tasks
and moves data at higher speeds than available
from current DMA controllers. Up to 16 MB may
be transferred with one instruction. T here are two
restrictions:
1. Both the source and destination addresses
must start with the same address alignment
(A(1-0) must be the same). If source and
destination are not aligned, then an illegal
instruction interrupt will occur. For the PCI
Cache Line Size register setting to take effect,
the source and destination must be the same
distance from a cache line boundary.
2. Indirect addresses are not allowed. A burst of
data is fetched from the source address, put
into the DMA FIFO and then written out to
the destination address. T he move continues
until the byte count decrements to zero, then
another SCRIPT is fetched from system
memory.
T he DSPS and DSA registers are additional hold-
ing registers used during the Memory Move; how-
ever, the contents of the DSA register are
preserved.
Bits 31-39Instruction Type—Memory Move
Bits 28-25 Reserved
T hese bits are reserved and must be zero. If
any of these bits is set, an illegal instruction
interrupt will occur.
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