參數(shù)資料
型號(hào)： SYM53C875
廠商： LSI Corporation
英文描述： PCI-Ultra SCSI I/O Processor(PCI-Ultra SCSI I/O處理器)
中文描述： 的PCI -超的SCSI I / O處理器（個(gè)PCI -超的SCSI的I / O處理器）
文件頁(yè)數(shù)： 129/243頁(yè)
文件大?。?/td> 1362K
代理商： SYM53C875
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SCSI Operating Registers
SYM53C875/875E Data Manual
5-43
Register 43 (C3)
SCSI Interrupt Status One (SIST 1)
Read Only
Reading the SIST 1 register returns the status of the
various interrupt conditions, whether they are en-
abled in the SIEN1 register or not. Each bit that is
set indicates the corresponding condition has oc-
curred.
Reading the SIST 1 will clear the interrupt condi-
tion.
Bits 7-3 Reserved
Bit 2
ST O (Selection or Reselection
T ime-out)
T he SCSI device which the SYM53C875 was
attempting to select or reselect did not respond
within the programmed time-out period. See
the description of the ST IME0 register, bits 3-
0, for more information on the time-out timer.
Bit 1
GE N (General Purpose T imer
E xpired)
T his bit is set when the general purpose timer
has expired. T he time measured is the time
between enabling and disabling of the timer.
See the description of the ST IME1 register,
bits 3-0, for more information on the general
purpose timer.
Bit 0
HT H (Handshake-to-Handshake
T imer E xpired)
T his bit is set when the handshake-to-hand-
shake timer has expired. T he time measured is
the SCSI Request-to-Request (target) or
Acknowledge-to-Acknowledge (initiator)
period. See the description of the ST IME0
register, bits 7-4, for more information on the
handshake-to-handshake timer.
Register 44 (C4)
SCSI Longitudinal Parity (SLPAR)
Read/Write
T he SLPAR register consists of two multiplexed
bytes; other register bit settings determine what is
displayed at this memory location at any given time.
When bit 5 in the SCNT L2 (SLPMD) register is
cleared, the chip X ORs the high and low bytes of
the SLPAR register together to give a single-byte
value which is displayed in the SLPAR register. If
the SLPMD bit is set, then the SLPAR register
shows either the high byte or the low byte of the
SLPAR word. T he SLPAR High Byte Enable bit,
SCNT L2 bit 4, determines which byte of the
SLPAR register is visible on the SLPAR register at
any given time. If this bit is cleared, the SLPAR reg-
ister contains the low byte of the SLPAR word; if it
is set, the SLPAR register contains the high byte of
the SLPAR word.
T his register performs a bytewise longitudinal par-
ity check on all SCSI data received or sent through
the SCSI core. If one of the bytes received or sent
(usually the last) is the set of correct even parity
bits, SLPAR should go to zero (assuming it started
at zero). As an example, suppose that the following
three data bytes and one check byte are received
from the SCSI bus (all signals are shown active
high):
A one in any bit position of the final SLPAR value
would indicate a transmission error.
T he SLPAR register can also be used to generate
the check bytes for SCSI send operations. If the
SLPAR register contains all zeros prior to sending
RES
7
RES
6
RES
5
RES
4
RES
3
STO
2
GEN
1
HTH
0
Default>>>
X
X
X
X
X
0
0
0
Data Bytes
Running SLPAR
---
1. 11001100
2. 01010101
3. 00001111
00000000
11001100 (X OR of word 1)
10011001 (X OR of word 1 and 2)
10010110 (X OR of word 1, 2 and 3)
Even Parity >>>10010110
00000000
4. 10010110
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