參數(shù)資料
型號(hào): ST623X-DBE
廠商: 意法半導(dǎo)體
英文描述: D/A Converter (D-A) IC; Resolution (Bits):24; Update Rate:192kSPS; No. of DACs:6; Data Interface:Serial; Package/Case:48-LQFP; Leaded Process Compatible:No; No. of Bits:24; No. of Channels:6; Operating Temp. Max:85 C RoHS Compliant: Yes
中文描述: 實(shí)時(shí)仿真開發(fā)工具,ST6單片機(jī)系列
文件頁數(shù): 71/86頁
文件大小: 531K
代理商: ST623X-DBE
71/86
ST62T30B ST62E30B
Opcode Map Summary
(Continued)
LOW
8
1000
HI
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
RNZ
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
2
JRNZ 4
e
1
pcr 2
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
LOW
HI
0
0000
JP 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
JRNC 4
e
pcr 2
RES 2
JRZ 4
LDI 2
JRC 4
LD
0
0000
abc
b0,rr
e
rr,nn
e
a,(y)
ext 1
JP 2
b.d 1
SET 2
pcr 3
JRZ 4
imm 1
DEC 2
prc 1
JRC 4
ind
LD
1
0001
1
0001
abc
b0,rr
e
x
e
a,rr
ext 1
JP 2
b.d 1
RES 2
pcr 1
JRZ 4
sd 1
prc 2
JRC 4
dir
CP
2
0010
COM 2
2
0010
abc
b4,rr
e
a
e
a,(y)
ext 1
JP 2
b.d 1
SET 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
CP
3
0011
LD 2
3
0011
abc
b4,rr
e
x,a
e
a,rr
ext 1
JP 2
b.d 1
RES 2
pcr 1
JRZ 2
sd 1
prc 2
JRC 4
dir
4
0100
RETI 2
ADD
4
0100
abc
b2,rr
e
e
a,(y)
ext 1
JP 2
b.d 1
SET 2
pcr 1
JRZ 4
inh 1
DEC 2
prc 1
JRC 4
ind
5
0101
ADD
5
0101
abc
b2,rr
e
y
e
a,rr
ext 1
JP 2
b.d 1
RES 2
pcr 1
JRZ 2
sd 1
prc 2
JRC 4
dir
6
0110
STOP 2
INC
6
0110
abc
b6,rr
e
e
(y)
ext 1
JP 2
b.d 1
SET 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
INC
7
0111
7
0111
abc
b6,rr
e
y,a
e
rr
ext 1
JP 2
b.d 1
RES 2
pcr 1
JRZ
sd 1
prc 2
JRC 4
dir
LD
8
1000
2
8
1000
abc
b1,rr
e
#
e
(y),a
ext 1
JP 2
b.d 1
SET 2
pcr
JRZ 4
1
prc 1
JRC 4
ind
LD
9
1001
4
DEC 2
9
1001
abc
b1,rr
e
v
e
rr,a
ext 1
JP 2
b.d 1
RES 2
pcr 1
JRZ 4
sd 1
RCL 2
prc 2
JRC 4
dir
A
1010
AND
A
1010
abc
b5,rr
e
a
e
a,(y)
ext 1
JP 2
b.d 1
SET 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
B
1011
AND
B
1011
abc
b5,rr
e
v,a
e
a,rr
ext 1
JP 2
b.d 1
RES 2
pcr 1
JRZ 2
sd 1
RET 2
prc 2
JRC 4
dir
C
1100
SUB
C
1100
abc
b3,rr
e
e
a,(y)
ext 1
JP 2
b.d 1
SET 2
pcr 1
JRZ 4
inh 1
DEC 2
prc 1
JRC 4
ind
D
1101
SUB
D
1101
abc
b3,rr
e
w
e
a,rr
ext 1
JP 2
b.d 1
RES 2
pcr 1
JRZ 2
sd 1
prc 2
JRC 4
dir
E
1110
WAIT 2
DEC
E
1110
abc
b7,rr
e
e
(y)
ext 1
JP 2
b.d 1
SET 2
pcr 1
JRZ 4
inh 1
LD 2
prc 1
JRC 4
ind
F
1111
DEC
F
1111
abc
b7,rr
e
w,a
e
rr
ext 1
b.d 1
pcr 1
sd 1
prc 2
dir
Abbreviations for Addressing Modes: Legend:
dir
Direct
sd
Short Direct
imm
Immediate
inh
Inherent
ext
Extended
b.d
Bit Direct
bt
Bit Test
pcr
Program Counter Relative
ind
Indirect
#
e
b
rr
nn
abc
ee
Indicates Illegal Instructions
5 Bit Displacement
3 Bit Address
1byte dataspace address
1 byte immediate data
12 bit address
8 bit Displacement
2
JRC
e
1
prc
Mnemonic
Addressing Mode
Bytes
Cycle
Operand
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