參數(shù)資料
型號: ST623X-DBE
廠商: 意法半導(dǎo)體
英文描述: D/A Converter (D-A) IC; Resolution (Bits):24; Update Rate:192kSPS; No. of DACs:6; Data Interface:Serial; Package/Case:48-LQFP; Leaded Process Compatible:No; No. of Bits:24; No. of Channels:6; Operating Temp. Max:85 C RoHS Compliant: Yes
中文描述: 實時仿真開發(fā)工具,ST6單片機(jī)系列
文件頁數(shù): 60/86頁
文件大小: 531K
代理商: ST623X-DBE
60/86
ST62T30B ST62E30B
5.4 U. A. R. T. (Universal Asynchronous Receiver/Transmitter)
The UART provides the basic hardware for asyn-
chronous serial communication which, combined
with anappropriate software routine, gives a serial
interface providing communication with common
baud rates (up to 38,400 Baud with an 8MHz ex-
ternal oscillator) and flexible character formats.
Operating in Half-Duplex mode only, the UART
uses 11-bitcharacterscomprising 1 start bit, 9 data
bits and 1 Stop bit. Parity is supported by software
only for transmitand for checking thereceived par-
ity bit(bit 9). Transmitteddata is sent directly,while
received data is buffered allowing further data
characters to be received while the data is being
read out of the receive buffer register. Data trans-
mit has priority over data being received.
The UART is supplied with an MCU internal clock
that isalsoavailableinWAITmodeoftheprocessor.
5.4.1 PORTS INTERFACING
RXD reception line and TXD emission line are
sharing the same external pins as two I/O lines.
Therefore, UART configuration requires to set
these two I/O lines through the relevant ports reg-
isters. The I/O line common with RXD line must be
defined as input mode (with or without pull-up)
while the I/O line common with TXD line must be
defined as output mode (Push-pull or open drain).
The transmitted data is inverted and can therefore
use a single transistor buffering stage. Defined as
input, the RXD line can be read at any time as an
I/O line during the UART operation. The TXD pin
follows I/O port registers value when UARTOE bit
is cleared, which means when no serial transmis-
sion is in progress. As a consequence, a perma-
nent highlevel hasto be written onto the I/O port in
order to achieve a proper stop condition on the
TXD line when no transmission is active.
Figure 34. UART Block Diagram
C
T
START
DETECTOR
DATA SHIFT
REGISTER
D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL REGISTER
BAUD RATE
RECEIVE BUFFER
REGISTER
PROGRAMMABLE
DIVIDER
DIN
DOUT
D9
BAUD RATE x 8
WRITE
READ
RXD1
TXD1
UARTOE
RX and TX
INTERRUPTS
TXD
DR
0
MUX
1
f
INT
VR02009
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