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參數資料
| 型號： | ST623X-DBE |
| 廠商： | 意法半導體 |
| 英文描述： | D/A Converter (D-A) IC; Resolution (Bits):24; Update Rate:192kSPS; No. of DACs:6; Data Interface:Serial; Package/Case:48-LQFP; Leaded Process Compatible:No; No. of Bits:24; No. of Channels:6; Operating Temp. Max:85 C RoHS Compliant: Yes |
| 中文描述： | 實時仿真開發(fā)工具，ST6單片機系列 |
| 文件頁數： | 33/86頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ST623X-DBE |
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ST62T30B ST62E30B
IINTERRUPTS
(Cont’d)
Interrupt Polarity Register (IPR)
Address: DAh
—
Read/Write
In conjunction with IOR register ESB bit, the polar-
ity of I/O pins triggered interrupts can be selected
by setting accordingly the Interrupt Polarity Regis-
ter (IPR). If a bit in IPR is set to one the corre-
sponding port interrupt is inverted (e.g. IPR bit 2 =
1 ; port C generates interrupt onrising edge. At re-
set, IPR is cleared and all portinterrupts arenot in-
verted (e.g. Port C generates interrupts on falling
edges).
Bit 7 - Bit 4 = Unused
Bit 3 = Port D Interrupt Polarity.
Bit 2 = Port C Interrupt Polarity.
Bit 1= Port A Interrupt Polarity
Bit 0 = Port B Interrupt Polarity.
Tables 12. I/O Interrupts selections according to IPR, IOR programming
7
0
-
-
-
-
PortD PortC PortA PortB
GEN
IPR3
IPR0
IOR5
Port B occurrence
Port D occurrence
Interrupt
source
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
falling edge
rising edge
rising edge
falling edge
falling edge
rising edge
rising edge
falling edge
Disabled
falling edge
rising edge
falling edge
rising edge
rising edge
falling edge
rising edge
falling edge
Disabled
2
GEN
IPR1
IOR6
Port A occurrence
Interrupt
source
1
1
1
1
0
0
0
1
1
X
0
1
0
1
X
falling edge
low level
rising edge
high level
Disabled
1
IPR2
0
1
Port C occurrence
falling edge
rising edge
Interrupt source
0
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