參數(shù)資料
型號(hào): ST623X-DBE
廠商: 意法半導(dǎo)體
英文描述: D/A Converter (D-A) IC; Resolution (Bits):24; Update Rate:192kSPS; No. of DACs:6; Data Interface:Serial; Package/Case:48-LQFP; Leaded Process Compatible:No; No. of Bits:24; No. of Channels:6; Operating Temp. Max:85 C RoHS Compliant: Yes
中文描述: 實(shí)時(shí)仿真開發(fā)工具,ST6單片機(jī)系列
文件頁(yè)數(shù): 45/86頁(yè)
文件大?。?/td> 531K
代理商: ST623X-DBE
45/86
ST62T30B ST62E30B
TIMER
(Cont’d)
5.1.1 Timer Operating Modes
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (f
INT
÷
12 or TIMER pin signal), and to
the output mode.
5.1.1.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
In this mode the prescaler is decremented by the
Timer clock input (f
INT
÷
12), but ONLY when the
signal on the TIMER pin is held high (allowing
pulse width measurement). This mode is selected
by clearing the TOUT bit in the TSCR register to
“0” (i.e. as input) and setting the DOUT bit to “1”.
5.1.1.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”)
In this mode, the TIMER pin is the input clock of
the prescaler which is decremented on the rising
edge.
5.1.1.3 Output Mode
(TOUT = “1”, DOUT = data out)
The TIMER pin is connected to the DOUT latch,
hence the Timer prescaler is clocked by the pres-
caler clock input (f
INT
÷
12).
The user can select the desired prescaler division
ratio through the PS2, PS1, PS0 bits. When the
TCR count reaches 0, it sets the TMZ bit in the
TSCR. The TMZ bit can be tested under program
control to perform a timer function whenever it
goes high. The low-to-high TMZ bit transition is
used to latch theDOUT bit of the TSCR and trans-
fer itto the TIMER pin. This operating mode allows
external signal generation on the TIMER pin.
Table 15. Timer Operating Modes
5.1.2 Timer Interrupt
When thecounter register decrements to zero with
the ETI (Enable Timer Interrupt) bit set to one, an
interrupt request is generated as described in the
Interrupt Chapter. When the counter decrements
to zero, the TMZ bit in the TSCR register is set to
one.
Figure 25. Timer Working Principle
TOUT
0
0
1
1
DOUT
0
1
0
1
Timer Pin
Input
Input
Output
Output
Timer Function
Event Counter
Gated Input
Output “0”
Output “1”
BIT0
BIT1
BIT2
BIT3
BIT6
BIT5
BIT4
CLOCK
7-BIT PRESCALER
8-1 MULTIPLEXER
8-BIT COUNTER
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
1
0
2
3
4
5
6
7
PS0
PS1
PS2
VA00186
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