參數(shù)資料
型號(hào)： ST623X-DBE
廠商： 意法半導(dǎo)體
英文描述： D/A Converter (D-A) IC; Resolution (Bits):24; Update Rate:192kSPS; No. of DACs:6; Data Interface:Serial; Package/Case:48-LQFP; Leaded Process Compatible:No; No. of Bits:24; No. of Channels:6; Operating Temp. Max:85 C RoHS Compliant: Yes
中文描述： 實(shí)時(shí)仿真開發(fā)工具，ST6單片機(jī)系列
文件頁(yè)數(shù)： 53/86頁(yè)
文件大?。?/td> 531K
代理商： ST623X-DBE
53/86
ST62T30B ST62E30B
TIMINGS MEASUREMENT MODES
(Cont’d)
5.2.3.2 Timing measurement without startup
control
The down counter is in free running mode with
RUNRES bit set and RELOAD bit cleared. This
means counter automatically restarts from FFFFh
on zero overflow and signal generation on PWM
and OVF pins is not affected.
Two independent capture paths exist to CP and
RLCP, which are both Read only registers. CP1 is
the source (Configurable polarity) for a capture
into RLCP while CP2 is the source (Configurable
polarity) of a capture into CP.
Independently of CP2 signal, if CP1FLG and
CP1ERR are cleared, the first active edge on CP1
will trigger a capture into RLCP, triggering
CP1FLG. As long as CP1FLG has not been
cleared, a second following active edge will trig
CP1ERR without any capture into neither RLCP
nor CP.
Independently of CP1 signal, if CP2FLG and
CP2ERR are cleared, the first active edge on CP2
will trigger a capture into CP, triggering CP2FLG.
As long as CP2FLG has not been cleared, a sec-
ond following active edge willtrig CP2ERR without
any capture into neither RLCP or CP.
5.2.4 INTERRUPT CAPABILITIES
The interrupt source latches of the ARTIMER16
are always enabled and set any time the interrupt
condition occurs.
The interrupt output is a logical OR of five logical
ANDs:
– INT = [(CP1FLG & CP1IEN)
– OR (CP2FLG & CP2IEN)
– OR(OVFFLG & OVFIEN)
– OR(COMPFLG & CMPIEN)
– OR (ZEROFLG & ZEROIEN)]
Thus, if any enable bit is 1, the interrupt output of
the ARTIMER16 goes high when the respective
flag is set. If no enable bit is 1, and one of the in-
terrupt flags is set, the interrupt output remains 0,
but if the respective enable bit is set to 1 througha
write operation, the interrupt output will go high,
signalling the interrupt to the Core.
Figure 32. Positive CP1 - to negative CP2-Edge Measurement (CP1POL = 1, CP2POL = 0)
Application Note:
Depending onpolarity setting for CP1/CP2, and of
CP1/CP2 connections, phase, period and pulse
width measurements can be achieved. The total
independence between CP1 and CP2 captures al-
lows phase detection by measuring which of
CP1FLG orCP2FLG is set at first following a reset
VR02006F
COUNTER
CP1
CP2
Capture into RLCP
Set CP1FLG
Set CP1ERR
Set CP2FLG
Capture into CP
Set CP2ERR
CP1=CP2
Yes
Yes
No
CP1POL=CP2POL
Yes
No
X
Measurement
Period
Pulse width
Phase
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