參數(shù)資料
型號: SM34020AHTM32
廠商: TEXAS INSTRUMENTS INC
元件分類: 圖形處理器
英文描述: GRAPHICS PROCESSOR, CQFP132
封裝: CERAMIC, QFP-132
文件頁數(shù): 84/98頁
文件大?。?/td> 1546K
代理商: SM34020AHTM32
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
85
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
CBR refresh: RAS and CAS0--CAS3 (see Note 5 and Figure 49)
The refresh pseudo-address present on LAD0--LAD31 is the output from the 16-bit refresh address
register([IO] register located at C000 01F0h) on LAD16--LAD31. LAD0--LAD3 have the refresh status code
(status code = 0011), and LAD4--LAD15 are held low.
NO
’34020A-32
’34020A-40
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
76
td(CK1L-REL)
Delay time, RAS low after LCLK1 no
longer high
tQ+12 + s
tQ+10 + s
ns
77
td(CK1L-REH)
Delay time, RAS high after LCLK1 no
longer high
tQ+12
tQ+10
ns
78
td(CK1H-CEL)
Delay time, CAS low after LCLK1 no
longer low
tQ+12
tQ+10
ns
79
td(CK1L-CEH)
Delay time, CAS high after LCLK1 no
longer high
tQ+12
tQ+10
ns
102
td(REL-CEH)
Delay time, RAS low to CAS no longer
low
4tQ--12 + s
4tQ -- 4+ s
ns
103
td(CEL-REL)
Delay time, CAS low to RAS no longer
high
2tQ--15
2tQ -- 13.5
ns
104
td(REH-CEL)
Delay time, RAS high to CAS no longer
high
2tQ--15 + s
2tQ --13.5+ s
ns
NOTE 5: s =tQ if using the clock stretch;
s = 0 otherwise
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