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| 型號： | SM34020AHTM32 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, CQFP132 |
| 封裝： | CERAMIC, QFP-132 |
| 文件頁數(shù)： | 59/98頁 |
| 文件大?。?/td> | 1546K |
| 代理商： | SM34020AHTM32 |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
62
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
cycle timing examples (continued)
Data transfer from a coprocessor to memory requires an initialization cycle to inform the coprocessor what is
to be transferred and then a memory cycle to perform the actual transfer (Figure 35). The coprocessor can place
status information on LAD during the initialization cycle for the SMJ34020A. The memory cycle includes a dead
cycle to enable the SMJ34020A to take LAD drivers to the high-impedance state before the coprocessor
activates its LAD bus drivers to the memory. Two types of memory-to-coprocessor instructions are supported.
Both provide a count (from 1 to 32) of data to be moved in the instruction. Both also specify a register to be used
as an index into memory. One uses this index register with a postincrement and the other uses it with a
predecrement after each transfer cycle.
LCLK1
LCLK2
CAMD
RCA
LAD
Q4
Q1
Q2
Q3
Q4
Q1 Q2
Q3
Q4
Q1
LAD
Command
Q2
Q3
Q1
SF
DDIN
Data 1
LRDY
BUSFLT
Address
Data 2
2nd Column
1st Column
Row
Q2
Q3
Q4 Q1 Q2
Q3
Q4
Q1
Q2
Q3
Q4
(TMS34020A)
(Coprocessor)
Status
GI
ALTCH
RAS
CAS
WE
TR/QE
DDOUT
PGMD
SIZE16
(see Note B)
R0
R1
Command Cycle
Address
Data Transfer
Spacer
Q4
(see Note A)
See clock stretch, page 21.
NOTES: A. LAD (SMJ34020A): Output to LAD by the SMJ34020A
LAD (coprocessor):
Output to LAD by the coprocessor
Command:
Coprocessor ID, instruction and status code present on LAD
Address:
Memory address for the data transfer, with coprocessor status code
Data n:
Data from the coprocessor (number of values transferred depends on a count in the instruction)
Status:
Optional coprocessor status register output to LAD bus
B. All coprocessor cycles are implemented as 32-bit operations; therefore, SIZE16 should be high during these cycles.
Figure 35. Transfer-Coprocessor Register(s) to Memory (ALTCH High During Data Transfer)
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