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參數(shù)資料
| 型號(hào)： | SM34020AHTM32 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, CQFP132 |
| 封裝： | CERAMIC, QFP-132 |
| 文件頁(yè)數(shù)： | 64/98頁(yè) |
| 文件大?。?/td> | 1546K |
| 代理商： | SM34020AHTM32 |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
67
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
signal transition levels (continued)
2.6 V
2V
1V
0.6 V
1.5 V
Figure 38. TTL-Level Outputs
TTL-level outputs are driven to a minimum logic-high level of 2.6 V and to a maximum logic-low level of 0.6 V.
For a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V, and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level
at which the output is said to be no longer low is 1 V, and the level at which the output is said to be high is 2 V.
AVOL trip level of 1.5 V is used for timing requirements for testing at -- 55°C.
test measurement
The test load circuit shown in Figure 39 represents the programmable load of the tester pin electronics that is
used to verify timing parameters of SMJ34020A output signals.
IOL
VLOAD
IOH
CLOAD
Test
Point
From Output
Under Test
Where:
IOL = 2 mA (all outputs)
IOH = 400 μA (all outputs)
VLOAD =1.5 V
CLOAD = 80 pF typical load circuit capacitance
NOTE: The load applied may be set higher than the values
indicated for IOL and IOH during timing tests in order to
reduce signal bounce induced by the tester hardware.
However the timing performance is assured at the stated
load values.
Figure 39. Test Load Circuit
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