參數(shù)資料
型號： SM34020AHTM32
廠商： TEXAS INSTRUMENTS INC
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, CQFP132
封裝： CERAMIC, QFP-132
文件頁數(shù)： 78/98頁
文件大?。?/td> 1546K
代理商： SM34020AHTM32
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME
TYPE
DESCRIPTION
VIDEO INTERFACE (CONTINUED)
HSYNC
I/O
Horizontal sync. HSYNC is the horizontal sync signal that controls external video circuitry. HSYNC can be
programmed to be either an input or an output by modifying a control bit in the DPYCTL register.
As an output, HSYNC is the active-low horizontal-sync signal generated by the SMJ34020A’s on-chip video
timers.
As an input, HSYNC synchronizes the SMJ34020A video-control registers to externally generated
horizontal-sync pulses. The actual synchronization can be programmed to begin at any VCLK cycle; this
allows for any external pipelining of signals.
Immediately following reset, HSYNC is configured as an input.
SCLK
I
Serial data clock. SCLK is the same as the signal that drives VRAM serial data registers. SCLK allows the
SMJ34020A to track the VRAM serial-data-register count, providing serial-register transfer and midline-reload
cycles. (SCLK can be asynchronous to VCLK; however, it typically has a frequency that is a multiple of the VCLK
frequency).
VCLK
I
Video clock. VCLK is derived from a multiple of the video system’s dot clock and is used internally to drive the video
timing logic.
VSYNC
I/O
Vertical sync. VSYNC is the vertical sync signal that controls external video circuitry. VSYNC can be programmed
to be either an input or an output by modifying a control bit in the DPYCTL register.
As an output, VSYNC is the active-low vertical-sync signal generated by the SMJ34020A’s on-chip video
timers.
As an input, VSYNC synchronizes the SMJ34020A video-control registers to externally generated
vertical-sync pulses. The actual synchronization can be programmed to begin at any horizontal line; this
allows for any external pipelining of signals.
Immediately following reset, VSYNC is configured as an input.
I = input, O = output
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