參數(shù)資料
型號： SM34020AHTM32
廠商： TEXAS INSTRUMENTS INC
元件分類： 圖形處理器
英文描述： GRAPHICS PROCESSOR, CQFP132
封裝： CERAMIC, QFP-132
文件頁數(shù)： 67/98頁
文件大?。?/td> 1546K
代理商： SM34020AHTM32
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
7
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME
TYPE
DESCRIPTION
POWER
VCC
I
Nominal 5-V power supply inputs. Five pins on QFP; Nine pins on PGA.
VSS
I
Electrical ground inputs. Nine pins on QFP; 17 pins on PGA.
EMULATION CONTROL
EMU0--EMU2
I
Emulation pins 0--2
EMU3
O
Emulation pin 3
MULTIPROCESSOR INTERFACE
GI
I
Bus grant input. External bus arbitration logic drives GI low to enable the SMJ34020A to gain access to the
local-memory bus. The SMJ34020A must release the bus if GI is high so that another device can access the bus.
R1, R0
O
Bus request and control. R1 and R0 indicate a request for use of the bus in a multiprocessor system; they are
decoded as shown below:
R1 R0
Bus Request Type
L
High-priority bus request
L
H
Bus-cycle termination
H
L
Low-priority bus request
H
No bus request pending
A high-priority bus request provides for VRAM serial-data-register transfer cycles (midline or blanked), DRAM
refresh (when 12 or more refresh cycles are pending), or a host-initiated access. The external arbitration logic
should grant the request as soon as possible by asserting GI low.
A low-priority bus request is used to provide for CPU-requested access and DRAM refresh (when less than
12 refresh cycles are pending).
Bus-cycle termination status is provided so that the arbitration logic can determine that the device currently
accessing the bus is completing an access, and other devices can compete for the next bus cycle. A
no-bus-request-pending status is output when the currently active device does not require the bus on subsequent
cycles.
VIDEO INTERFACE
CBLNK / VBLNK
O
Composite blanking/vertical blanking. CBLNK / VBLNK can be programmed to select one of two blanking
functions:
Composite blanking for blanking the display during both horizontal and vertical retrace periods in
composite-sync-video mode
Vertical blanking for blanking the display during vertical retrace in separate-sync-video mode.
Immediately following reset, CBLNK / VBLNK is configured as a CBLNK output.
CSYNC / HBLNK
I/O
Composite sync/horizontal blanking. CSYNC /HBLNK can be programmed to select one of two functions:
Composite sync (either input or output as set by a control bit in the DPYCTL register) in
composite-sync-video mode:
As an input, extracts HSYNC and VSYNC from externally generated horizontal sync pulses
As an output, CSYNC /HBLNK generates active-low composite-sync pulses from either externally
generated HSYNC and VSYNC signals or signals generated by the SMJ34020A’s on-chip video timers
Horizontal blank (output only) for blanking the display during horizontal retrace in separate-sync-video
mode.
Immediately following reset, CSYNC /HBLNK is configured as a CSYNC input.
I = input, O = output
For proper SMJ34020A operation, all VCC and VSS pins must be connected externally.
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