參數(shù)資料
型號: SM34020AHTM32
廠商: TEXAS INSTRUMENTS INC
元件分類: 圖形處理器
英文描述: GRAPHICS PROCESSOR, CQFP132
封裝: CERAMIC, QFP-132
文件頁數(shù): 44/98頁
文件大小: 1546K
代理商: SM34020AHTM32
SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
cycle timing examples (continued)
Two SMJ34020As use the multiprocessor interface to pass control of local memory from one to the other
(Figure 26). GSP1 completes a read cycle to the local memory and, although desiring another read, loses the
bus to GSP2, which does a single write cycle (perhaps a host-write access). GSP1 then regains control and
completes the read cycle (shown with a single wait state). Since no further memory-access requests are
present, GSP1 maintains control of the bus and holds all of the local-memory control signals at their inactive
levels. LRDY is a common input to both GSP1 and GSP2.
The host cycle timing diagrams shown in this data sheet are only a sample. For more information, see the
TMS34020 User’s Guide.
12 3 4 12 3 4 12 3 4 12 3 4
1
12 3 4 12 3 4 12 3 4 12 3 4
1
GSP1 Read
GSP2 Write
GSP1 Read With Wait
Bus Idle
GSP1
GI
R0
R1
RAS
CAS
WE
TR/QE
DDIN
DDOUT
ALTCH
LRDY
ALTCH
GI
R0
R1
RAS
CAS
WE
TR/QE
DDIN
DDOUT
GSP2
Figure 26. Multiprocessor-Interface Cycle Timing (Passing Control)
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