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參數(shù)資料
| 型號(hào)： | SM34020AHTM32 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 圖形處理器 |
| 英文描述： | GRAPHICS PROCESSOR, CQFP132 |
| 封裝： | CERAMIC, QFP-132 |
| 文件頁(yè)數(shù)： | 25/98頁(yè) |
| 文件大?。?/td> | 1546K |
| 代理商： | SM34020AHTM32 |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
cycle timing examples (continued)
The refresh pseudo-address output to RCA0--RCA12 and LAD0--LAD31 comes from the 16-bit refresh
address register (I/O register C000 01F0h) that is incremented after each refresh cycle (Figure 13). The 16 bits
of address are placed on LAD16--LAD31; all other LAD bus lines are zero. The logical addresses on
RCA0--RCA12 corresponding to LAD16--LAD31 also output the address from the refresh-address register.
Although PGMD and SIZE16 are ignored during a refresh cycle, they should be held at valid levels. LRDY and
BUSFLT are not sampled until the start of the first Q2 cycle after RAS has gone low.
If a refresh cycle is aborted due to a high-priority bus request (assuming LRDY is low at Q2 after RAS low), a
bus fault, or an external retry, then the count of refreshes pending is not decremented and the same
pseudo-address is reissued when the refresh is restarted.
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