參數(shù)資料
型號(hào): SM320F2812HFGM
廠商: TEXAS INSTRUMENTS INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝: NCTB, CERAMIC, QFP-172
文件頁(yè)數(shù): 70/147頁(yè)
文件大?。?/td> 1721K
代理商: SM320F2812HFGM
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Functional Overview
29
December 2004
SGUS053
3.2.6
Flash
The F2812 contains 128K x 16 of embedded flash memory, segregated into four 8K X 16 sectors, and six 16K
X 16 sectors. The F2810 has 64K X 16 of embedded flash, segregated into two 8K X 16 sectors, and three
16K X 16 sectors. The device also contains a single 1K x 16 of OTP memory at address range 0x3D 7800
0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors
untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms
that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve
higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to
execute code or store data information.
NOTE:
The F2812 Flash and OTP wait states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash
options register. With this mode enabled, effective performance of linear code execution will
be much faster than the raw performance indicated by the wait state configuration alone. The
exact performance gain when using the Flash pipeline mode is application-dependent. The
pipeline mode is not available for the OTP block.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see
the TMS320x281x System Control and Interrupts Reference Guide (literature number
SPRU078).
3.2.7
L0, L1, H0 SARAMs
The F281x contains an additional 16K x 16 of single-access RAM, divided into 3 blocks (4K + 4K + 8K). Each
block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to both program
and data space.
3.2.8
Boot ROM
The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after
device reset and checks several GPIO pins to determine which boot mode to enter. For example, the user can
select to execute code already present in the internal Flash or download new software to internal RAM through
one of several serial ports. Other boot modes exist as well. The Boot ROM also contains standard tables, such
as SIN/COS waveforms, for use in math-related algorithms. Table 33 shows the details of how various boot
modes may be invoked. See the TMS320x281x DSP Boot ROM Reference Guide (literature number
SPRS095), for more information.
Table 33. Boot Mode Selection
MODE
DESCRIPTION
GPIO18
SPICLKA
SCITXB
GPIO29
SCITXA
GPIO34
Boot to Flash
Jump to Flash address 0x3F 7FF6
A branch instruction here must have been pro-
grammed prior to reset to redirect code execution
as desired.
1
SCIA Boot
Load a data stream from SCIA.
1
0
SPIA Boot
Load from an external serial SPI EEPROM on
SPIA.
1
0
1
I2C Boot
Load data from an external EEPROM at address
0x50 on the I2C bus.
1
0
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