參數(shù)資料
型號： SM320F2812HFGM
廠商： TEXAS INSTRUMENTS INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝： NCTB, CERAMIC, QFP-172
文件頁數(shù)： 56/147頁
文件大?。?/td> 1721K
代理商： SM320F2812HFGM
Introduction
16
December 2004
SGUS053
Table 22. Signal Descriptions (Continued)
NAME
DESCRIPTION
PU/PD§
I/O/Z
PIN
NO.
NAME
DESCRIPTION
PU/PD§
I/O/Z
172-PIN
HFG
XINTF SIGNALS (CONTINUED)
XMP/MC
17
I
PD
Microprocessor/Microcomputer
Mode
Select.
Switches
between
microprocessor and microcomputer mode. When high, Zone 7 is enabled on the
external interface. When low, Zone 7 is disabled from the external interface, and
on-chip boot ROM may be accessed instead. This signal is latched into the
XINTCNF2 register on a reset and the user can modify this bit in software. The
state of the XMP/MC pin is ignored after reset.
XHOLD
155
I
PU
External Hold Request. XHOLD, when active (low), requests the XINTF to
release the external bus and place all buses and strobes into a high-impedance
state. The XINTF will release the bus when any current access is complete and
there are no pending accesses on the XINTF.
XHOLDA
80
O/Z
External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses and strobe signals will be in a
high-impedance state. XHOLDA is released when the XHOLD signal is
released. External devices should only drive the external bus when XHOLDA is
active (low).
XZCS0AND1
43
O/Z
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active (low) when an
access to the XINTF Zone 0 or Zone 1 is performed.
XZCS2
86
O/Z
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an access to the XINTF
Zone 2 is performed.
XZCS6AND7
130
O/Z
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active (low) when an
access to the XINTF Zone 6 or Zone 7 is performed.
XWE
82
O/Z
Write Enable. Active-low write strobe. The write strobe waveform is specified,
per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers.
XRD
41
O/Z
Read Enable. Active-low read strobe. The read strobe waveform is specified,
per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers.
NOTE: The XRD and XWE signals are mutually exclusive.
XR/W
50
O/Z
Read Not Write Strobe. Normally held high. When low, XR/W indicates write
cycle is active; when high, XR/W indicates read cycle is active.
XREADY
157
I
PU
Ready Signal. Indicates peripheral is ready to complete the access when
asserted to 1. XREADY can be configured to be a synchronous or an
asynchronous input. See the timing diagrams for more details.
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
75
I
Oscillator Input input to the internal oscillator. This pin is also used to feed an
external clock. The 28x can be operated with an external clock source, provided
that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted
that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core digital power
supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A clamping diode may
be used to clamp a buffered clock signal to ensure that the logic-high level does
not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
X2
74
O
Oscillator Output
XCLKOUT
117
O
Output clock derived from SYSCLKOUT to be used for external wait-state
generation and as a general-purpose clock source. XCLKOUT is either the
same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At
reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by
setting bit 3 (CLKOFF) of the XINTCNF2 register to 1.
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
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