參數資料
型號: SM320F2812HFGM
廠商: TEXAS INSTRUMENTS INC
元件分類: 數字信號處理
英文描述: 16-BIT, 150 MHz, OTHER DSP, CQFP172
封裝: NCTB, CERAMIC, QFP-172
文件頁數: 142/147頁
文件大?。?/td> 1721K
代理商: SM320F2812HFGM
Electrical Specifications
94
December 2004
SGUS053
tw(RSL1)
th(XPLLDIS)
th(XMP/MC)
th(boot-mode)
(see Note D)
VDDIO,VDD3VFL
VDDAn,V
DDAIO
(3.3 V)
(See Note B)
XCLKIN
2.5 V
0.3 V
X1
XRS
XF/XPLLDIS
XMP/MC
Boot-Mode Pins
VDD, VDD1
(1.8 V (or 1.9 V))
XCLKOUT
I/O Pins
User-Code Dependent
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
GPIO Pins as Input
XPLLDIS Sampling
GPIOF14
XCLKIN/8 (See Note C)
GPIO Pins as Input (State Depends on Internal PU/PD)
tOSCST
(Don’t Care)
User-Code Dependent
Address/Data/
Control
Address/Data Valid. Internal Boot-ROM Code Execution Phase
User-Code Execution Phase
NOTES: A. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least
1 V and 3.3-V supply reaches 2.5 V.
B. VDDAn VDDA1/VDDA2 and AVDDREFBG
C. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the
XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This
explains why XCLKOUT = XCLKIN/8 during this phase.
D. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then
samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot
code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM
execution time for proper selection of Boot modes.
If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on
the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL
enabled.
td(EX)
See NOTE
tsu(XPLLDIS)
Figure 68. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A)
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