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參數(shù)資料
型號(hào)： SI3200-BS
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 64/128頁(yè)
文件大小： 0K
描述： IC LINEFEED INTRFC 100V 16SOIC
標(biāo)準(zhǔn)包裝： 48
系列： ProSLIC®
功能： 用戶線路接口概念（SLIC），CODEC
接口： GCI，PCM，SPI
電路數(shù)： 2
電源電壓： 3.3V，5V
電流 - 電源： 110µA
功率（瓦特）： 941mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm Width）裸露焊盤
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
包括： 電池切換，BORSCHT 功能，DTMF 生成和解碼，F(xiàn)SK 音調(diào)生成，調(diào)制解調(diào)器和傳真音調(diào)檢測(cè)
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Si3232
40
Preliminary Rev. 0.96
Not
Recommended
fo
r N
ew
D
esi
gn
s
which the RING lead oscillates. The dc offset is set at a
dc point equal to VCM – (–80 V + VOFF), where VOFF is
the value that is input into the RINGOF RAM location.
Positive VOFF values cause the dc offset point to move
closer to ground (lower dc offset), and negative VOFF
values have the opposite effect. The dc offset can be
set to any value; however, the ringing signal is clipped
digitally if the dc offset is set to a value that is less than
half the ringing amplitude. In general, the following
equation must hold true to ensure the battery voltage is
sufficient to provide the desired ringing amplitude:
|VBATR| > |VRING,PK + (–80 V + VOFF) + VOVRING|
It is possible to create reverse polarity unbalanced
ringing waveforms (the TIP lead oscillates while the
RING lead stays constant) by setting the UNBPOLR bit
of the RINGCON register. In this mode, the polarity of
VOFF must also be reversed (in normal ringing polarity,
VOFF is subtracted from –80 V, and in reverse polarity,
ringing VOFF is added to –80 V).
4.7.1. Ringing Coefficients
The ringing coefficients are calculated in decimal for
sinusoidal and trapezoidal waveforms. The RINGPHAS
and
RINGAMP
hex
values
are
decimal-to-hex
conversions in 16-bit, 2’s complement representations
for their respective RAM locations.
To obtain sinusoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to a 24-bit 2’s
complement value. The lower 12 bits are placed in
RINGFRLO bits 14:3. RINGFRLO bits 15 and 2:0 are
cleared to 0. The upper 12 bits are set in a similar
manner in RINGFRHI, bits 13:3. RINGFRHI bit 14 is the
sign bit and RINGFRHI bits 2:0 are cleared to 0.
For
example,
the
register
values
for
RINGFREQ = 0x7EFD9D are as follows:
RINGFRHI = 0x3F78
RINGFRLO = 0x6CE8
To obtain trapezoidal RINGFREQ RAM values, the
RINGFREQ decimal number is converted to an 8-bit, 2’s
complement value. This value is loaded into RINGFRHI.
RINGFRLO is not used.
Figure 19. Trapezoidal Ringing Waveform
4.7.2. Ringing DC Offset Voltage
A dc offset voltage can be added to the Si3232’s ac
ringing waveform by programming the RINGOF RAM
address to the appropriate setting. The value of
RINGOF is calculated as follows:
4.7.3. Linefeed Overhead Voltage Considerations
During Ringing
The ringing mode output impedance allows ringing
operation
without
overhead
voltage
modification
(VOVR = OV). If an offset of the ringing signal from the
RING lead is desired, VOVR can be used for this
purpose.
4.7.4. Ringing Power Considerations
The total power consumption of the Si3232/Si3200
chipset using internal ringing generation is dependent
on the VDD supply voltage, the desired ringing
amplitude, the total loop impedance, and the ac load
impedance (number of REN). The following equations
can be used to approximate the total current required
for each channel during ringing mode.
Where:
time
V OFF
T=1/freq
tRISE
VTIP-RING
RINGOF
V
OFF
160.8
---------------
2
15
=
I
DD,AVE
V
RING,PK
Z
LOOP
-----------------------
2
---
I
DD,OH
+
=
I
BAT,AVE
V
RING,PK
Z
LOOP
-----------------------
2
---
=
V
RING,PK
V
RING,RMS
2
=
Z
LOOP
R
LOOP
R
LOAD
R
OUT
++
=
R
LOAD
7000
REN
------------- (for North America)
=
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SI3200-BSR 制造商:Silicon Laboratories Inc 功能描述:
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SI3200-FSR 制造商:Silicon Laboratories Inc 功能描述:SLIC 2CH 70DB 45MA 3.3V/5V 16SOIC EP - Tape and Reel
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SI3200-G-FSR 功能描述:電信線路管理 IC 100 V Linefeed Interface RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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