參數(shù)資料
型號(hào): S29GL128P11FAIR10
廠商: SPANSION LLC
元件分類: DRAM
英文描述: 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述: 128M X 1 FLASH 3V PROM, 110 ns, PBGA64
封裝: 13 X 11 MM, 1 MM PITCH, FBGA-64
文件頁(yè)數(shù): 62/77頁(yè)
文件大小: 2121K
代理商: S29GL128P11FAIR10
62
S29GL-P MirrorBit
Flash Family
S29GL-P_00_A7 November 8, 2007
D a t a
S h e e t
( P r e l i m i n a r y )
Figure 11.11
Chip/Sector Erase Operation Timings
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see
Write Operation Status on page 36
.)
2. These waveforms are for the word mode
Figure 11.12
Data# Polling Timings (During Embedded Algorithms)
Notes
1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
2. t
OE
for data polling is 45 ns when V
IO
= 1.65 to 2.7 V and is 35 ns when V
IO
= 2.7 to 3.6 V
3. CE# does not need to go high between status bit reads
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
t
RB
t
BUSY
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ6–DQ0
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
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