參數(shù)資料
型號： S29GL064N11BAIV12
廠商： Spansion Inc.
英文描述： 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
中文描述： 64兆，32兆位3.0伏只頁面模式閃存具有110納米MirrorBit工藝技術(shù)
文件頁數(shù)： 59/79頁
文件大?。?/td> 2191K
代理商： S29GL064N11BAIV12
November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit
Flash Family
59
D a t a
S h e e t
Figure 10.6 on page 58
shows the toggle bit algorithm in flowchart form.
Figure 15.9 on page 70
shows the
toggle bit timing diagram.
Figure 15.10 on page 70
shows the differences between DQ2 and DQ6 in graphical
form.
10.15 Reading Toggle Bits DQ6/DQ2
Refer to
Figure 10.6 on page 58
for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device completed the program or erase operation. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, the device successfully completed the program or erase
operation. If it is still toggling, the device did not completed the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of
Figure 10.6 on page 58
).
10.16 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or write-to-buffer time exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a
1
. indicating that the program or erase cycle was not
successfully completed.
The device may output a
1
on DQ5 if the system tries to program a
1
to a location that was previously
programmed to
0
.
Only an erase operation can change a
0
back to a
1.
Under this condition, the device
halts the operation, and when the timing limit is exceeded, DQ5 produces a
1
.
In all these cases, the system must write the reset command to return the device to the reading the array (or
to erase-suspend-read if the device was previously in the erase-suspend-program mode).
10.17 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not
erasure began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after each additional sector erase command. When the
time-out period is complete, DQ3 switches from a
0
to a
1
. If the time between additional sector erase
commands from the system can be assumed to be less than 50 μs, the system need not monitor DQ3. See
also the Sector Erase Command Sequence section.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device accepted the command sequence, and then read DQ3. If DQ3 is
1
, the
Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the
erase operation is complete. If DQ3 is
0
, the device accepts additional sector erase commands. To ensure
the command is accepted, the system software should check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on the second status check, the last command might not
have been accepted.
Table 10.5 on page 60
shows the status of DQ3 relative to the other status bits.
相關(guān)PDF資料
PDF描述
S29GL064N11BAIV20 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BAIV22 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BAIV60 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BAIV62 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
S29GL064N11BFI010 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology
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