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參數(shù)資料
| 型號： | S29GL064N11BAIV12 |
| 廠商： | Spansion Inc. |
| 英文描述： | 64 Megabit, 32 Megabit 3.0-Volt only Page Mode Flash Memory Featuring 110 nm MirrorBit Process Technology |
| 中文描述： | 64兆，32兆位3.0伏只頁面模式閃存具有110納米MirrorBit工藝技術(shù) |
| 文件頁數(shù)： | 19/79頁 |
| 文件大?。?/td> | 2191K |
| 代理商： | S29GL064N11BAIV12 |
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November 16, 2007 S29GL-N_01_09
S29GL-N MirrorBit
Flash Family
19
D a t a
S h e e t
8.4
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V
IO
± 0.3 V.
(Note that this is a more restricted voltage range than V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
IO
± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
standard access time (t
CE
) for read access when the device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Refer to the
DC Characteristics
on page 62
for the standby current specification.
8.5
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+ 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Refer to the
DC
Characteristics
on page 62
for the automatic sleep mode current specification.
8.6
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
RP
, the device immediately terminates any operation in
progress, Hi-Z all output pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC5
). If RESET# is held at V
IL
but not within V
SS
±0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to
Figure 15.4 on page 66
for the timing
diagram.
8.7
Output Disable Mode
When the OE# input is at V
IH
, output from the device is disabled. The output pins are placed in the high
impedance state.
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參數(shù)描述 |
|---|---|
| S29GL064N11DAIV10 | 制造商:Spansion 功能描述:64M (4MX16) 3V REG, MIRRORBIT, - Trays |
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| S29GL064N11FFIV20 | 制造商:Spansion 功能描述: |
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