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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 91/108頁 |
| 文件大?。?/td> | 992K |
| 代理商： | S1C621C0D |
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S1C621C0 TECHNICAL MANUAL
EPSON
75
CHAPTER 5: SUMMARY OF NOTES
(7)
When performing remote output in the hard-timer mode, do not write data to the ROUT3–ROUT0
register while the
τ waveform is high to prevent malfunction. Furthermore, next transmission data
writing should be done after the current carrier output is completed unless done intentionally. If this
register is written during carrier output, it stops output at that point of the falling edge of the
τ
waveform after the writing and starts new carrier output.
Furthermore, the ROUT3–ROUT0 register is for the exclusive use of the hard-timer mode. When
controlling with the soft-timer mode, be sure not to write data to this register to prevent malfunction.
(8)
When performing remote output in the hard-timer mode, do not write data to the RIC3–RIC0 register
while
τ waveform is high to prevent malfunction. If this register is re-written before generating the
interrupt corresponding the previous written data, the interrupt counter is renewed and the previous
set interrupt becomes invalid.
Furthermore, the RIC3–RIC0 register is for the exclusive use of the hard-timer mode. When controlling
with the soft-timer mode, be sure not to write data to this register to prevent malfunction.
(9)
The soft-timer mode and the hard-timer mode can not be used at the same time. To use them in
combination, set both REMCR and REMDC registers to "0" to stop the REM circuit before switching
the mode.
R/F converter
(1) Depending on the initial value of the measurement counter (MC), the measurement counter (MC) or the
time base counter may overflow while the CR oscillation clock is being counted. When setting the initial
value, pay attention to CR oscillation frequency, its fluctuation range and the input clock frequency of
the time base counter. If an overflow occurs, R/F conversion is terminated immediately. When the R/F
conversion result (measurement counter value) is read, check the overflow flags (OVMC and OVTBC).
(2) When an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag
(OVMC or OVTBC) is not reset. Be sure to check and reset to "0" (writing "1") the overflow flag when
the R/F converter interrupt occurs.
(3) When using the OSC3 clock as the time base counter input clock, the OSC3 oscillation circuit must be
ON (OSCC = "1") before starting R/F conversion.
It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes.
Consequently, when starting a remote output, secure 5 msec or more waiting time for oscillation
stabilization after turning the OSC3 oscillation ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics and
conditions of use, so allow ample margin when setting the waiting time.
SVD circuit
(1) To obtain a stable SVD detection result, the SVD circuit must be on for at least l00 sec. So, to obtain the
SVD detection result, follow the programming sequence below.
Set SVDON to "1"
Maintain for 100 sec minimum
Set SVDON to "0"
Read SVDDT
However, when fOSC1 is selected for CPU system clock, the instruction cycles are long enough, so there
is no need to worry about maintaining 100 sec for SVDON = "1" in the software.
(2) The SVD circuit should normally be turned OFF as the consumption current of the IC becomes large
when it is ON.
Interrupt and HALT
(1) The interrupt factor flags are set when the timing condition is established, even if the interrupt mask
registers are set to "0".
(2) Reading of interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will
not be generated.
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