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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 90/108頁 |
| 文件大?。?/td> | 992K |
| 代理商： | S1C621C0D |
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74
EPSON
S1C621C0 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
(3) When BZ and FOUT are selected, a hazard may be observed in the output waveform when the data of
the output register changes.
(4) When selecting fOSC3 as the FOUT clock frequency, it is necessary to control the OSC3 oscillation circuit.
See Section 4.3, "Oscillation Circuit" for details of the control.
I/O ports
When input terminals are changed from low to high by pull up resistor, the rise of the waveform is delayed
on account of the time constant of the pull up resistor and input gate capacitance. Hence, when fetching
data during input mode, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
Waiting time = RIN
× (CIN + load capacitance on board) × 1.6 [sec]
RIN: pull up resistance (Max. value)
CIN: terminal capacitance (Max. value)
LCD driver
(1) The contents of the display memory are undefined until the area is initialized (through, for instance,
memory clear processing by the CPU). Initialize the display memory by executing initial processing.
(2) When page 4 is selected for the display memory area, since the display memory area is write-only,
display data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB).
(3) 100 msec or more time is necessary for stabilizing the LCD drive voltages VC1, VC2 and VC3 after setting
the LCD power control register LPWR to "1". Be careful of the segment-on right after the power is
turned on.
Clock timer
(1) Be sure to data reading in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).
(2) When the clock timer has been reset, the interrupt factor flag (IT) may sometimes be set to "1". Conse-
quently, perform flag reading (reset the flag) as necessary at reset.
Remote controller
(1)
When using the remote control outputs, fix the R00 and R01 registers at "0" and do not change them.
(If the REMDC output is not used, the R01 register and terminal can be used as an output port.)
(2)
Except when outputting the remote control waveform, both REMCR and REMDC registers should be
fixed at "0" to prevent outputting unnecessary waveform and to reduce current consumption.
(3)
When performing remote output, it is necessary that the OSC3 oscillation circuit has already been ON.
Remote output should be started when the OSC3 oscillation is stabilized.
It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi-
lizes. Consequently, when starting a remote output, secure 5 msec or more waiting time for oscillation
stabilization after turning the OSC3 oscillation ON.
Further, the oscillation stabilization time varies depending ON the external oscillator characteristics
and conditions of use, so allow ample margin when setting the waiting time.
(4)
The setting of the RCDIV register (carrier cycle), RCDTY register (carrier duty ratio) and RT1/RT0
registers (
τ reference cycle) should be done when the REM circuit is OFF (REMCR = REMDC = "0")
before starting remote transmission. Changing the contents when the REM circuit is ON may cause a
malfunction.
(5)
When performing remote output in the soft-timer mode, be sure to control the carrier output using the
REMSO register. Do not control the carrier output using the REMCR register by setting the REMSO
register to "1". Similarly, in the case of REMDC output, do not control the output using the REMDC
register.
(6)
REMSO is for the exclusive use of the soft-timer mode. When controlling with the hard-timer mode,
REMSO should be fixed at "0".
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