S1C621C0 TECHNICAL MANUAL
EPSON
65
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit)
4.11.3 Control of SVD circuit
Table 4.11.3.1 shows the control bits and their addresses for the SVD circuit.
Table 4.11.3.1 Control bits for SVD circuit
*1 Initial value at the time of initial reset
*5 Constantly "0" when being read
*2 Not set in the circuit
*6 Refer to main manual
*3 Undefined
*7 Page switching in I/O memory is not necessary
*4 Reset (0) immediately after being read
SVDON: SVD circuit ON/OFF (80HD0)
Turns the SVD circuit ON and OFF.
When "1" is written:
SVD circuit ON
When "0" is written:
SVD circuit OFF
Reading:
Valid
When SVDON is set to "1", source voltage detection by the SVD circuit is executed. As soon as SVDON is
reset to "0", the result is loaded to in the SVDDT latch. To obtain a stable SVD detection result, the SVD
circuit must be on for at least l00 sec.
At initial reset, this register is set to "0".
SVDDT: SVD data (80HD1)
This is the result of supply voltage detection.
When "0" is read:
Supply voltage (VDD–VSS)
≥ Criteria voltage
When "1" is read:
Supply voltage (VDD–VSS) < Criteria voltage
Writing:
Invalid
The result of supply voltage detection at time of SVDON is set to "0" can be read from this latch.
At initial reset, SVDDT is set to "0".
4.11.4 Programming notes
(1) To obtain a stable SVD detection result, the SVD circuit must be on for at least l00 sec. So, to obtain the
SVD detection result, follow the programming sequence below.
Set SVDON to "1"
Maintain for 100 sec minimum
Set SVDON to "0"
Read SVDDT
However, when fOSC1 is selected for CPU system clock, the instruction cycles are long enough, so there
is no need to worry about maintaining 100 sec for SVDON = "1" in the software.
(2) The SVD circuit should normally be turned OFF as the consumption current of the IC becomes large
when it is ON.
Address
Comment
Register
D3
D2
D1
D0
Name
Init
1
0
*1
SVDON
R/W
0
SVDDT
SVDON
–
0
Low
On
Normal
Off
SVDDT
0
R
0
80H
*2
*5
*7
Unused
Supply voltage detection data
SVD circuit On/Off