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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 7/108頁 |
| 文件大小： | 992K |
| 代理商： | S1C621C0D |
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96
EPSON
S1C621C0 TECHNICAL MANUAL
APPENDIX D: COMMAND TABLE OF ICE
APPENDIX
D. COMMAND TABLE OF ICE
1
2
3
4
5
6
7
8
9
10
Assemble
Disassemble
Dump
Fill
Set
Run Mode
Trace
Break
Move
Data Set
Change CPU
Internal
Registers
#A,a
#L,a1,a2
#DP,a1,a2
#DD,a1,a2
#FP,a1,a2,d
#FD,a1,a2,d
#G,a
#TIM
#OTF
#T,a,n
#U,a,n
#BA,a
#BAR,a
#BD
#BDR
#BR
#BRR
#BM
#BMR
#BRES
#BC
#BE
#BSYN
#BT
#BRKSEL,REM
#MP,a1,a2,a3
#MD,a1,a2,a3
#SP,a
#SD,a
#DR
#SR
#I
#DXY
#SXY
Assemble command mnemonic code and store at address "a"
Contents of addresses a1 to a2 are disassembled and displayed
Contents of program area a1 to a2 are displayed
Content of data area a1 to a2 are displayed
Data d is set in addresses a1 to a2 (program area)
Data d is set in addresses a1 to a2 (data area)
Program is executed from the "a" address
Execution time and step counter selection
On-the-fly display selection
Executes program while displaying results of step instruction
from "a" address
Displays only the final step of #T,a,n
Sets Break at program address "a"
Breakpoint is canceled
Break condition is set for data RAM
Breakpoint is canceled
Break condition is set for Evaluation Board CPU internal registers
Breakpoint is canceled
Combined break conditions set for program data RAM address
and registers
Cancel combined break conditions for program data ROM
address and registers
All break conditions canceled
Break condition displayed
Enter break enable mode
Enter break disable mode
Set break stop/trace modes
Set BA condition clear/remain modes
Contents of program area addresses a1 to a2 are moved to
addresses a3 and after
Contents of data area addresses a1 to a2 are moved to addresses
a3 and after
Data from program area address "a" are written to memory
Data from data area address "a" are written to memory
Item No.
Function
Command Format
Outline of Operation
Display Evaluation Board CPU internal registers
Set Evaluation Board CPU internal registers
Reset Evaluation Board CPU
Display X, Y, MX and MY
Set data for X and Y display and MX, MY
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