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參數(shù)資料
| 型號： | S1C621C0D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74 |
| 封裝： | DIE-74 |
| 文件頁數(shù)： | 60/108頁 |
| 文件大?。?/td> | 992K |
| 代理商： | S1C621C0D |
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S1C621C0 TECHNICAL MANUAL
EPSON
47
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller)
(3) Remote controller (REM) interrupt
The carrier output ON time for one transmission data bit is controlled by writing data to the above
mentioned ROUT3–ROUT0 register. The OFF time is from when the output is turned OFF to when the
next carrier output starts by writing to the same register. Since the carrier output is turned ON at the
falling edge of the
τ waveform after writing data, the next data must be written during the last τ cycle
in the carrier OFF period of the current transmission data. To decide its timing, an interrupt is used in
the hard-timer mode.
By using the interrupt, the CPU is released from the processing such as a timing watch, and can execute
other processing.
The timing to generate interrupt can be set by the software using
τ cycle as reference the same as the
carrier output width. Set the interrupt timing so that it will be generated after 1 to 16
τ cycles, and
perform the next carrier output using the interrupt.
The interrupt timing can be selected by writing data to the RIC3–RIC0 register (E2H) from among 16
types as shown in Table 4.9.5.4.
Table 4.9.5.4 Setting of interrupt timing
RIC3
0
1
RIC2
0
1
0
1
Interrupt
τ cycle
1
τ
2
τ
3
τ
4
τ
5
τ
6
τ
7
τ
8
τ
9
τ
10
τ
11
τ
12
τ
13
τ
14
τ
15
τ
16
τ
RIC1
0
1
0
1
0
1
0
1
RIC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
* Interrupt cycle n
τ: The interrupt is generated at the falling
(n=1 to 16)
edge of the selected
τ pulse after writing
the RIC register.
When the REM circuit has been turned ON (REMCR/REMDC = "1"), the REM interrupt control circuit
starts counting for
τ waveform at the point that data is written to the RIC3–RIC0 register. The τ wave-
form is counted at every falling edge. When the count becomes the number set in the RIC3–RIC0
register, the interrupt factor flag IREM (F8HD0) is set to "1" and an interrupt occurs in synchronization
with that falling edge.
Set the next carrier output width and the interrupt timing using this interrupt.
The REM interrupt can be masked through the interrupt mask register EIREM (F1HD0). However,
regardless of the setting of the interrupt mask register, the interrupt factor flag IREM is set to "1" when
the counting of the interrupt
τ cycles are completed.
The interrupt factor flag is reset to "0" by the reading.
Data written to the RIC3–RIC0 register is maintained while the REM circuit is ON until the next data is
written. However, the counting of
τ waveform starts using the write signal for the RIC3–RIC0 register
the same as the ROUT3–ROUT0 register, so this register data is valid only one time after writing.
Consequently, data must be written (possible with a logical arithmetic instruction) every time even
when generating the next interrupt in the same cycle.
The RIC3–RIC0 register is set to "0FH" (16
τ) at initial reset and when both REMCR and REMDC regis-
ters are set to "0". However, the counting of
τ cycles is not performed until the RIC3–RIC0 register is
written after that.
Figure 4.9.5.3 shows the timing of data writing to the RIC3–RIC0 register and the interrupt generation.
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