參數(shù)資料
型號: S1C621C0D
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 1.3 MHz, MICROCONTROLLER, UUC74
封裝: DIE-74
文件頁數(shù): 64/108頁
文件大?。?/td> 992K
代理商: S1C621C0D
S1C621C0 TECHNICAL MANUAL
EPSON
51
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Remote Controller)
RIC3–RIC0: Interrupt
τ cycle selection (E2H)
When controlling in the hard-timer mode, select the interrupt generation timing.
Table 4.9.6.5 Setting of interrupt timing
RIC3
0
:
1
RIC2
0
:
1
Interrupt
τ cycle
1
τ
2
τ
3
τ
:
15
τ
16
τ
RIC1
0
1
:
1
RIC0
0
1
0
:
0
1
By writing data to this register when the REM circuit has been ON (REMCR/REMDC = "1"), the counting
of
τ waveform is started by synchronizing with the falling edge of the τ waveform immediately after that.
When the count becomes the number set in this register, an interrupt occurs. Set the next transmission data
and interrupt timing using this interrupt.
The setting (writing) of interrupt
τ cycle must be done at every bit of the transmission data.
At initial reset and when both REMCR and REMDC registers are set to "0", this register is set to "0FH
(1111B)".
Note: The RIC3–RICO register is for the exclusive use of the hard-timer mode. When controlling with the
soft-timer mode, be sure not to write data to this register to prevent malfunction.
EIREM: Interrupt mask register (F0HD0)
This register is used to select whether to mask the remote controller interrupt.
When "1" is written:
Enabled
When "0" is written:
Masked
Reading:
Valid
When "1" is written to EIREM, the remote controller interrupt is enabled. When "0" is written, it is masked.
At initial reset, this register is set to "0".
IREM: Interrupt factor flag (F8HD0)
This is the interrupt factor flag of the remote controller.
When "1" is read:
Interrupt has occurred
When "0" is read:
Interrupt has not occurred
Writing:
Invalid
This flag is set to "1" when the interrupt
τ cycle set with RIC3–RIC0 has passed (counting of the τ waveform
has completed).
From the status of this flag, the software can decide the remote controller interrupt. Note, however, that
even if the interrupt is masked, this flag will be set to "1" when the counting of the interrupt
τ cycle is
completed.
This flag is reset when read out by the software.
Reading of the interrupt factor flag is available at EI, but be careful in the following cases.
If the interrupt mask register value corresponding to the interrupt factor flag to be read is set to "1", an
interrupt request will be generated by the interrupt factor flag set timing, or an interrupt request will not be
generated.
At initial reset, this flag is set to "0".
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