- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372063 > RJ80530MY650256 MICROPROCESSOR|32-BIT|CMOS|BGA|479PIN|CERAMIC PDF資料下載
參數(shù)資料
| 型號(hào)： | RJ80530MY650256 |
| 元件分類： | 微處理器 |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|479PIN|CERAMIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 479PIN |陶瓷 |
| 文件頁(yè)數(shù)： | 36/89頁(yè) |
| 文件大小： | 1672K |
| 代理商： | RJ80530MY650256 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)當(dāng)前第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)
Mobile Intel
Pentium
III Processor-M Datasheet
36
Datasheet
298340-002
Table 20. System Bus Clock AC Specifications (133 MHz, Single Ended)
1
Symbol
Parameter
Min
Max
Unit
Figure
Notes
System Bus Frequency
133
MHz
T1S
BCLK Period
7.5
7.65
ns
6
Note 2
T1Sabs
BCLK Period – Instantaneous
Minimum
7.25
Note 2
T2S
BCLK Period Stability
±250
ps
Notes 2, 3, 4
T3S
BCLK High Time
1.4
ns
6
at>2.0V
T4S
BCLK Low Time
1.4
ns
6
at<0.5V
T5S
BCLK Rise Time
0.4
1.6
ns
6
Note 5
T6S
NOTES:
1.
All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25V.
2.
Period, jitter, skew and offset measured at 1.25V.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a
component of BCLK skew between devices.
5.
Measured between 0.5V and 2.0V.
BCLK Fall Time
0.4
1.6
ns
6
Note 5
Table 21. System Bus Clock AC Specifications (100 MHz, Single Ended)
1
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
System Bus Frequency
100
MHz
T1S1
BCLK Period
10
ns
6
Note 2
T1S1abs BCLK Period – Instantaneous
Minimum
9.75
ns
Note 2
T2S1
BCLK Period Stability
±250
ps
Notes 2, 3, 4
T3S1
BCLK High Time
2.70
ns
6
at>2.0V
T4S1
BCLK Low Time
2.45
ns
6
at<0.5V
T5S1
BCLK Rise Time
0.4
1.6
ns
6
Note 5
T6S1
NOTES:
1.
All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1.25V.
2.
Period, jitter, skew and offset measured at 1.25V.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a
component of BCLK skew between devices.
5.
Measured between 0.5V and 2.0V.
BCLK Fall Time
0.4
1.6
ns
6
Note 5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RJ80530NZ001256 | Microprocessor |
| RJ80530VY700256 | Microprocessor |
| RJ80530VZ733256 | Microprocessor |
| RHFL4913 | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| RHFL4913S50-04V | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RJ80530MZ001256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| RJ80530MZ001256S L798 | 制造商:Intel 功能描述:32BIT MPU 80530MZ001256 1.00G |
| RJ80530MZ733256 | 制造商:Rochester Electronics LLC 功能描述:MOBILE CELERON 733MHZ, 256K - Bulk |
| RJ80530MZ733256S L6B4 | 制造商:Intel 功能描述:MPU Celeron 制造商:Intel 功能描述:MPU Celeron? Processor 64-Bit 0.13um 733MHz 478-Pin uFCPGA |
| RJ80530MZ866256 | 制造商:Rochester Electronics LLC 功能描述:32BIT MPU - Bulk 制造商:Intel 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。