參數(shù)資料
型號: PPXY8300A6T1
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: Pressure Sensor
英文描述: DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝: SOIC-20
文件頁數(shù): 95/162頁
文件大?。?/td> 4316K
代理商: PPXY8300A6T1
MPXY8300 Series
Sensors
38
Freescale Semiconductor
5.9.6
System Oscillator Trim Register (SOTRM)
This register is used to trim the medium frequency internal oscillator.
5.9.7
System Device Identification Register (SDIDH, SDIDL)
This read-only register is included so host development systems can identify the HCS08 derivative and revision number. This
allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target
MCU.
Figure 5-8 System Device Identification Register — High (SDIDH)
Table 5-8 SOPT2 Register Field Descriptions
Field
Description
7
TRE
Temperature Restart Wakeup Enable — The TRE bit is used to enable the temperature restart wake-up.
0
Temperature restart wake-up disabled
1
Temperature restart wake-up enabled
6:4
COPT[2:0]
COP Watchdog Time-out — These write-once bits select the time-out period of the COP. COPT, along with
COPCLKS in SOPT1, defines the COP time-out period. See Table 5-1.
3
LFOSEL
LFO Selected — LFOSEL determines which signal is connected to the TPM channel 0.
0
TPMEH0 clock input driven by PTA2
1
TPMEH0 clock input driven by LFO
2
TCLKDIV
Timer Clock Divider — This write once bit determines the divide ratio of the external clock source, TPMCLK.
0
Divide by 1
1
Divide by 8
1:0
BUSCLKS[1:0]
Bus Clock Select — HFO divide by:
00 Divide by 2
01 Divide by 4
10 Divide by 8
11 Divide by 16
7
6
5
4
3
2
1
0
R SOTRM7
SOTRM6
SOTRM5
SOTRM4
SOTRM3
SOTRM2
SOTRM1
SOTRM0
W
Loaded from NVM at reset
X
Figure 5-7 System Oscillator Trim Register (SOTRM)
Table 5-9 SOTRM Register Field Descriptions
Field
Description
7:0
SOTRM[7:0]
MFO Trim Value — The SOTRM bits are used to trim the frequency of the medium frequency oscillator. Frees-
cale will factory program a FLASH location with this trim value. Upon reset, the FLASH location is read and
transferred to this register. Users should not modify this register. Erasure of FLASH will not change the trim
value in FLASH.
7
6
5
4
3
2
1
0
R
ID11
ID10
ID9
ID8
W
Reset:
0(1)
NOTES:
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
0(1)
0
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