參數(shù)資料
型號(hào): PPXY8300A6T1
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: Pressure Sensor
英文描述: DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝: SOIC-20
文件頁(yè)數(shù): 79/162頁(yè)
文件大?。?/td> 4316K
代理商: PPXY8300A6T1
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)當(dāng)前第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)
MPXY8300 Series
Sensors
Freescale Semiconductor
23
Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with a background debug
command while the MCU is secured (The background debug controller can only do blank check and mass erase
commands when the MCU is secure.)
Writing 0 to FCBEF to cancel a partial command
4.6.6
FLASH Block Protection
The block protection feature prevents the protected region of FLASH from program or erase changes. Block protection is
controlled through the FLASH Protection Register (FPROT). When enabled, block protection begins at any 512 byte boundary
below the last address of FLASH, 0xFFFF. (see Section 4.8.4).
After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the nonvolatile register block of the
FLASH memory. FPROT cannot be changed directly from application software so a runaway program cannot alter the block
protection settings. Because NVPROT is within the last 512 bytes of FLASH, if any amount of memory is protected, NVPROT is
itself protected and cannot be altered (intentionally or unintentionally) by the application software. FPROT can be written through
background debug commands which allows a way to erase and reprogram a protected FLASH memory.
The block protection mechanism is illustrated below. The FPS bits are used as the upper bits of the last address of unprotected
memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits as shown. For example, in order to protect the
last 8192 bytes of memory (addresses 0xE000 through 0xFFFF), the FPS bits must be set to 1101 111 which results in the value
0xDFFF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit
0 of NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be programmed into
NVPROT to protect addresses 0xE000 through 0xFFFF.
Figure 4-4 Block Protection Mechanism
One use for block protection is to block protect an area of FLASH memory for a bootloader program. This bootloader program
then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact
even if MCU power is lost in the middle of an erase and reprogram operation.
4.6.7
Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector redirection allows users to
modify interrupt vector information without unprotecting bootloader and reset vector space. Vector redirection is enabled by
programming the FNORED bit in the NVOPT register located at address 0xFFBF to zero. For redirection to occur, at least some
portion but not all of the FLASH memory must be block protected by programming the NVPROT register located at address
0xFFBD. All of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector (0xFFFE:FFFF)
is not.
For example, if 512 bytes of FLASH are protected, the protected address region is from 0xFE00 through 0xFFFF. The interrupt
vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. Now, if an SPI interrupt is taken for instance, the
values in the locations 0xFDE0:FDE1 are used for the vector instead of the values in the locations 0xFFE0:FFE1. This allows
the user to reprogram the unprotected portion of the FLASH with new program code including new interrupt vector values while
leaving the protected area, which includes the default vector locations, unchanged.
4.7
Security
The MPXY8300 Series includes circuitry to prevent unauthorized access to the contents of FLASH and RAM memory. When
security is engaged, FLASH and RAM are considered secure resources. Direct-page registers, high-page registers, and the
background debug controller are considered unsecured resources. Programs executing within secure memory have normal
access to any MCU memory locations and resources. Attempts to access a secure memory location with a program executing
from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in the FOPT register.
During reset, the contents of the nonvolatile location NVOPT are copied from FLASH into the working FOPT register in high-page
register space. A user engages security by programming the NVOPT location, which can be done at the same time the FLASH
memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased
state (1:1) makes the MCU secure. During development, whenever the FLASH is erased, it is good practice to immediately
FPS7
FPS6
FPS5
FPS4
FPS3
FPS2
FPS1
A15
A14
A13
A12
A11
A10
A9
A8
1
A7 A6 A5 A4 A3 A2 A1 A0
111
11111
相關(guān)PDF資料
PDF描述
PR35MT2 RECTANGULAR ADAPTER
PR406-BCR5HD T-1 3/4 SINGLE COLOR LED, RED, 4.6 mm
PR44-PCG28H-CG SINGLE COLOR LED, GREEN, 6.35 mm
PRADA1-07F-BR000 ROCKER SWITCH, DPST, LATCHED, 7A, PANEL MOUNT
PRADD1-07F-BB000 ROCKER SWITCH, DPST, LATCHED, 7A, PANEL MOUNT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPYY12C0.75 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, PER M, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket Material:PVC (Polyvinyl Chloride), External Diameter:9.9mm,
PPYY12C0.75 100M 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 100M 制造商:PRIVATE LABEL 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Met 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 100M, Reel Length (Imperial):328ft, Reel Length (Metric):100m, No. of Conductors:12, Voltage Rating:500V, No. of Max Strands x Strand Size:-, Conductor Area CSA:0.75mm2, Jacket Colour:Grey, Jacket , RoHS Compliant: Yes
PPYY12C0.75 50M 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 50M
PPYY12C1.50 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, PER M
PPYY12C1.50 50M 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, 50M