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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 110/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
51
SECTION 8 CENTRAL PROCESSING UNIT
8.1
Introduction
This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08
Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor
document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced
addressing modes were added to improve C compiler efficiency and to support a new background debug system which replaces
the monitor mode of earlier M68HC08 microcontrollers (MCU).
8.1.1
Features
Features of the HCS08 CPU include:
Object code fully upward-compatible with M68HC05 and M68HC08 Families
All registers and memory are mapped to a single 64-Kbyte address space
16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
16-bit index register (H:X) with powerful indexed addressing modes
8-bit accumulator (A)
Many instructions treat X as a second general-purpose 8-bit register
Seven addressing modes:
–
Inherent — Operands in internal registers
–
Relative — 8-bit signed offset to branch destination
–
Immediate — Operand in next object code byte(s)
–
Direct — Operand in memory at 0x0000–0x00FF
–
Extended — Operand anywhere in 64-Kbyte address space
–
Indexed relative to H:X — Five submodes including auto increment
–
Indexed relative to SP — Improves C efficiency dramatically
Memory-to-memory data move instructions with four address mode combinations
Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed,
unsigned, and binary-coded decimal (BCD) operations
Efficient bit manipulation instructions
Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
STOP and WAIT instructions to invoke low-power operating modes
8.2
Programmer’s Model and CPU Registers
Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map.
Figure 8-1 CPU Registers
SP
PC
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
H
X
0
7
15
70
ACCUMULATOR
A
INDEX REGISTER (LOW)
INDEX REGISTER (HIGH)
STACK POINTER
87
PROGRAM COUNTER
16-BIT INDEX REGISTER H:X
CCR
C
V1 1 H I N Z
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