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MPXY8300 Series
Sensors
Freescale Semiconductor
133
background mode rather than executing the tagged instruction. When the TRGSEL control bit in the DBGT register is set to select
tag-type operation, the output from comparator A or B is qualified by a block of logic in the debug module that tracks opcodes
and only produces a trigger to the debugger if the opcode at the compare address is actually executed. There is separate opcode
tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time.
15.3.5
Trigger Modes
The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register selects one of nine trigger
modes. When TRGSEL = 1 in the DBGT register, the output of the comparator must propagate through an opcode tracking circuit
before triggering FIFO actions. The BEGIN bit in DBGT chooses whether the FIFO begins storing data when the qualified trigger
is detected (begin trace), or the FIFO stores data in a circular fashion from the time it is armed until the qualified trigger is detected
(end trigger).
A debug run is started by writing a 1 to the ARM bit in the DBGC register, which sets the ARMF flag and clears the AF and BF
flags and the CNT bits in DBGS. A begin-trace debug run ends when the FIFO gets full. An end-trace run ends when the selected
trigger event occurs. Any debug run can be stopped manually by writing a 0 to ARM or DBGEN in DBGC.
In all trigger modes except event-only modes, the FIFO stores change-of-flow addresses. In event-only trigger modes, the FIFO
stores data in the low-order eight bits of the FIFO.
The BEGIN control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. When TRGSEL = 1
to select opcode fetch triggers, it is not necessary to use R/W in comparisons because opcode tags would only apply to opcode
fetches that are always read cycles. It would also be unusual to specify TRGSEL = 1 while using a full mode trigger because the
opcode value is normally known at a particular address.
The following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. Either comparator can
usually be further qualified with R/W by setting RWAEN (RWBEN) and the corresponding RWA (RWB) value to be matched
against R/W. The signal from the comparator with optional R/W qualification is used to request a CPU breakpoint if BRKEN = 1
and TAG determines whether the CPU request will be a tag request or a force request.
A-Only — Trigger when the address matches the value in comparator A
A OR B — Trigger when the address matches either the value in comparator A or the value in comparator B
A Then B — Trigger when the address matches the value in comparator B but only after the address for another cycle matched
the value in comparator A. There can be any number of cycles after the A match and before the B match.
A AND B Data (Full Mode) — This is called a full mode because address, data, and R/W (optionally) must match within the same
bus cycle to cause a trigger event. Comparator A checks address, the low byte of comparator B checks data, and R/W is checked
against RWA if RWAEN = 1. The high-order half of comparator B is not used.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B
data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the
comparator A address matches.
A AND NOT B Data (Full Mode) — Address must match comparator A, data must not match the low half of comparator B, and
R/W must match RWA if RWAEN = 1. All three conditions must be met within the same bus cycle to cause a trigger.
In full trigger modes it is not useful to specify a tag-type CPU breakpoint (BRKEN = TAG = 1), but if you do, the comparator B
data match is ignored for the purpose of issuing the tag request to the CPU and the CPU breakpoint is issued when the
comparator A address matches.
Event-Only B (Store Data) — Trigger events occur each time the address matches the value in comparator B. Trigger events
cause the data to be captured into the FIFO. The debug run ends when the FIFO becomes full.
A Then Event-Only B (Store Data) — After the address has matched the value in comparator A, a trigger event occurs each
time the address matches the value in comparator B. Trigger events cause the data to be captured into the FIFO. The debug run
ends when the FIFO becomes full.
Inside Range (A
≤ Address ≤ B) — A trigger occurs when the address is greater than or equal to the value in comparator A and
less than or equal to the value in comparator B at the same time.
Outside Range (Address < A or Address > B) — A trigger occurs when the address is either less than the value in comparator
A or greater than the value in comparator B.
15.3.6
Hardware Breakpoints
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions described in
Section 15.3.5,to be used to generate a hardware breakpoint request to the CPU. TAG in DBGC controls whether the breakpoint request will be
treated as a tag-type breakpoint or a force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters
the instruction queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active
background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current
instruction and then go to active background mode.