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參數(shù)資料
| 型號(hào)： | PPXY8300A6T1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | Pressure Sensor |
| 英文描述： | DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 147/162頁 |
| 文件大?。?/td> | 4316K |
| 代理商： | PPXY8300A6T1 |
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MPXY8300 Series
Sensors
Freescale Semiconductor
85
11.4
PWU Control/Status Register 1 - PWUCS1
The PWUSC1 register contains six bits to select the division of the incoming RCLK clock period and provide interrupt flag and
acknowledge bits as described in Figure 11-4.
6
WUFACK
Wake-Up Interrupt Flag Acknowledge — The WUFACK bit clears the WUF bit if written with a one. Writing a
zero to the WUFACK bit has no effect on the WUF bit. Reading the WUFACK bit returns a zero. Reset has no
effect on this bit.
0
No effect
1
Clear WUF bit
5:0
WUT
Wake-Up Time Interval — These control bits select the number of WCLK clocks that are needed before the
next wake-up interrupt is generated. The count gives a range of wake-up times from 1 to 63 WCLK clocks.
Depending on the value of the bits for the WDIV0:5 this time interval can nominally be from 1 to 63 seconds in 1
second steps. Whenever the WUT0:5 bits are changed the prescaler, wake-up interrupt counter and periodic
reset counters are restarted. Writing the same data to the WUT0:5 bits has no effect.
Writing zeros to all of the WUT0:5 bits forces the wake-up divider to a value of $3F and disables the wake-up
interrupt. However, writing all zeros to the WUT0:5 bits is inhibited if all of the PRST0:5 bits are already cleared
to zero. This prevents disabling both the periodic wake-up and the periodic reset at the same time as shown in
The WUT0:5 bits are preset to a value of $3F (decimal 63) by any resets.
Table 11-3 Limitations on Clearing WUT/PRST
Control Bits
State of
Control Bits
Control Bits to be
Cleared
Resulting Action
Resulting
Wake-Up Interrupt
Resulting
Periodic Reset
WUT0:5
non-zero
PRST0:5
Allowed
Enabled(1)
NOTES:
1. Using previous values.
Disabled
all zero
Inhibited
Disabled(2)
2. Wake-up divider preset to $3F.
PRST0:5
non-zero
WUT0:5
Allowed
Disabled
all zero
Inhibited
Enabled(1)
Disabled
$003A
Bit 7
6
5
4
3
2
1
Bit 0
R
PRF
0
PRST
W
PRFACK
RESET:
0
1
Figure 11-4 PWU Control/Status Register 1 (PWUCS1)
Table 11-4 LFCS1 Register Field Descriptions
Field
Description
7
PRF
Periodic Reset Flag — The PRF bit indicates when a periodic reset has been generated by the PWU. MCU
writes to this bit have no effect. This bit is cleared by writing a one to the PRFACK bit. This bit is cleared by a
power on reset, but is unaffected by other resets.
Periodic reset not generated or previously acknowledged
Periodic reset generated
Table 11-2 LFCS1 Register Field Descriptions (Continued)
Field
Description
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| PPYY12C0.75 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 0.75MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 0.75MM, 50M |
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| PPYY12C1.50 50M | 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM 50M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, 50M |
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