參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 88/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
Freescale Semiconductor
31
recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are
difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR, A, X, and PC registers
to their pre-interrupt values by reading the previously saved information off the stack.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first.
NOTE
For compatibility with the M68HC08, the H register is not automatically saved and restored. It is good
programming practice to push H onto the stack at the start of the interrupt service routine (ISR) and restore it just
before the RTI that is used to return from the ISR.
5.4.1
Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer (SP) points at the next
available byte location on the stack. The current values of CPU registers are stored on the stack starting with the low-order byte
of the program counter (PCL) and ending with the CCR. After stacking, the SP points at the next available location on the stack
which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address
of the instruction in the main program that would have executed next if the interrupt had not occurred.
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part of the RTI sequence,
the CPU fills the instruction pipeline by reading three bytes of program information, starting from the PC address just recovered
from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR. Typically, the flag should be
cleared at the beginning of the ISR so that if another interrupt is generated by this same source, it will be registered so it can be
serviced after completion of the current ISR.
Figure 5-1 Interrupt Stack Frame
5.4.2
Interrupt Vectors, Sources and Local Masks
Table 5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the bottom of the table (at the
higher vector addresses). All of these vectors are 2-byte values of the user’s destination address. The actual hardware interrupt
vectors are located at $FFC0:FFFF. This allows the firmware to intercept all vectors and add additional processing as needed.
When an interrupt condition occurs, an associated flag bit becomes set in a globally assigned parameter register at location
$005F. The additional process latency and flag bit for each interrupt are described in Codewarrior project files supplied by
Freescale.
If the associated local interrupt enable is set, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask
(I bit in the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU registers, set the I bit,
and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service
routine.
The triggering of any of these vector fetches will wake-up the MCU from any of the stop or wait modes.
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER* (LOW BYTE X)
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
UNSTACKING
ORDER
STACKING
ORDER
SP before
the interrupt
SP after
interrupt stacking
Toward HIGHER Addresses
Toward LOWER Addresses
70
1
2
3
4
5
4
3
2
1
* High byte (H) of index register is not automatically stacked.
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