參數(shù)資料
型號： PPXY8300A6T1
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： Pressure Sensor
英文描述： DIFFERENTIAL, PEIZORESISTIVE PRESSURE SENSOR, RECTANGULAR, SURFACE MOUNT
封裝： SOIC-20
文件頁數(shù)： 41/162頁
文件大?。?/td> 4316K
代理商： PPXY8300A6T1
MPXY8300 Series
Sensors
Freescale Semiconductor
135
15.4.1.2
BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS control bits in BDCSCR
are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are
used to read and write the BDCBKPT register but is not accessible to user programs because it is not located in the normal
memory map of the MCU. Breakpoints are normally set while the target MCU is in active background mode before running the
user application program. For additional information about setup and use of the hardware breakpoint logic in the BDC, refer to
15.4.2
System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background mode command such as WRITE_BYTE must be used
to write to SBDFR. Attempts to write this register from a user program are ignored. Reads always return 0x00.
4
FTS
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0
Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1
Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode)
3
CLKSW
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC
clock source.
0
Alternate BDC clock source
1
MCU bus clock
2
WS
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function.
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into active back-
ground mode, the host should issue a READ_STATUS command to check that BDMACT = 1 before attempting
other BDC commands.
0
Target CPU is running user application code or in active background mode (was not in wait or stop mode
when background became active)
1
Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop
to active background mode
1
WSF
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACK-
GROUND command to get out of wait or stop mode into active background mode, repeat the command that
failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction.)
0
Memory access did not conflict with a wait or stop instruction
1
Memory access command failed because the CPU entered wait or stop mode
0
DVF
Data Valid Failure Status — This status bit is not used in the MPXY8300 Series because it does not have any
slow access memory.
0
Memory access did not conflict with a slow memory access
1
Memory access command failed because CPU was not finished with a slow memory access
Table 15-2 BDCSCR Register Field Descriptions (Continued)
Field
Description
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PPYY12C1.50 制造商:Farnell / Pro-Power 功能描述:CABLE YY 12 CORE 1.5MM PER M 制造商:pro-power 功能描述:CABLE, YY, 12 CORE, 1.5MM, PER M
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