TM Family Datasheet Page 7 of 79 June 2009 – R" />
參數(shù)資料
型號： PI7C9X20404GPBNBE
廠商： Pericom
文件頁數(shù)： 67/79頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 7 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
7.2.59
EEPROM CONTROL REGISTER – OFFSET DCh (Upstream Port Only)........................................ 47
7.2.60
EEPROM ADDRESS REGISTER – OFFSET DCh (Upstream Port Only)......................................... 48
7.2.61
EEPROM DATA REGISTER – OFFSET DCh (Upstream Port Only)................................................ 48
7.2.62
PCI EXPRESS CAPABILITY ID REGISTER – OFFSET E0h ............................................................ 48
7.2.63
NEXT ITEM POINTER REGISTER – OFFSET E0h .......................................................................... 49
7.2.64
PCI EXPRESS CAPABILITIES REGISTER – OFFSET E0h .............................................................. 49
7.2.65
DEVICE CAPABILITIES REGISTER – OFFSET E4h ....................................................................... 49
7.2.66
DEVICE CONTROL REGISTER – OFFSET E8h............................................................................... 50
7.2.67
DEVICE STATUS REGISTER – OFFSET E8h................................................................................... 51
7.2.68
LINK CAPABILITIES REGISTER – OFFSET ECh ............................................................................ 51
7.2.69
LINK CONTROL REGISTER – OFFSET F0h.................................................................................... 52
7.2.70
LINK STATUS REGISTER – OFFSET F0h ........................................................................................ 53
7.2.71
SLOT CAPABILITIES REGISTER (Downstream Port Only) – OFFSET F4h ................................... 53
7.2.72
SLOT CONTROL REGISTER (Downstream Port Only) – OFFSET F8h........................................... 54
7.2.73
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h ............................................... 55
7.2.74
PCI EXPRESS ADVANCED ERROR REPORTING CAPABILITY ID REGISTER – OFFSET 100h. 56
7.2.75
CAPABILITY VERSION – OFFSET 100h .......................................................................................... 56
7.2.76
NEXT ITEM POINTER REGISTER – OFFSET 100h......................................................................... 56
7.2.77
UNCORRECTABLE ERROR STATUS REGISTER – OFFSET 104h ................................................. 56
7.2.78
UNCORRECTABLE ERROR MASK REGISTER – OFFSET 108h .................................................... 57
7.2.79
UNCORRECTABLE ERROR SEVERITY REGISTER – OFFSET 10Ch............................................. 58
7.2.80
CORRECTABLE ERROR STATUS REGISTER – OFFSET 110 h...................................................... 59
7.2.81
CORRECTABLE ERROR MASK REGISTER – OFFSET 114 h ......................................................... 59
7.2.82
ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h......................... 60
7.2.83
HEADER LOG REGISTER – OFFSET From 11Ch to 128h .............................................................. 60
7.2.84
PCI EXPRESS VIRTUAL CHANNEL CAPABILITY ID REGISTER – OFFSET 140h ....................... 60
7.2.85
CAPABILITY VERSION – OFFSET 140h .......................................................................................... 60
7.2.86
NEXT ITEM POINTER REGISTER – OFFSET 140h......................................................................... 61
7.2.87
PORT VC CAPABILITY REGISTER 1 – OFFSET 144h .................................................................... 61
7.2.88
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h .................................................................... 61
7.2.89
PORT VC CONTROL REGISTER – OFFSET 14Ch........................................................................... 61
7.2.90
PORT VC STATUS REGISTER – OFFSET 14Ch............................................................................... 62
7.2.91
VC RESOURCE CAPABILITY REGISTER (0) – OFFSET 150h........................................................ 62
7.2.92
VC RESOURCE CONTROL REGISTER (0) – OFFSET 154h ........................................................... 62
7.2.93
VC RESOURCE STATUS REGISTER (0) – OFFSET 158h................................................................ 63
7.2.94
VC RESOURCE CAPABILITY REGISTER (1) – OFFSET 15Ch ....................................................... 63
7.2.95
VC RESOURCE CONTROL REGISTER (1) – OFFSET 160h ........................................................... 64
7.2.96
VC RESOURCE STATUS REGISTER (1) – OFFSET 164h................................................................ 64
7.2.97
VC ARBITRATION TABLE REGISTER – OFFSET 170h................................................................... 64
7.2.98
PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and 1C0h ........................... 65
7.2.99
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER – OFFSET 20Ch .................... 65
7.2.100
CAPABILITY VERSION – OFFSET 20Ch...................................................................................... 66
7.2.101
NEXT ITEM POINTER REGISTER – OFFSET 20Ch .................................................................... 66
7.2.102
DATA SELECT REGISTER – OFFSET 210h ................................................................................. 66
7.2.103
POWER BUDGETING DATA REGISTER – OFFSET 214h .......................................................... 66
7.2.104
POWER BUDGET CAPABILITY REGISTER – OFFSET 218h ..................................................... 67
8
CLOCK SCHEME .............................................................................................................................................68
9
HOT PLUG OPERATION ................................................................................................................................69
10 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER....................................................................................70
10.1
INSTRUCTION REGISTER ......................................................................................................................70
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