參數資料
| 型號： | PI7C9X20404GPBNBE |
| 廠商： | Pericom |
| 文件頁數： | 62/79頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 產品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標準包裝： | 189 |
| 系列： | GreenPacket™ |
| 應用： | 封裝開關，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 148-LFBGA |
| 供應商設備封裝： | 148-LFBGA（12x12） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 65 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
The VC arbitration table is a read-write register array that contains a table for VC arbitration. Each
table entry allocates four bits, of which three bits are used to represent VC ID and one bit is reserved.
A total of 32 entries are used to construct the VC arbitration table. The layout for this register array is
shown below.
Table 7-1 Register Array Layout for VC Arbitration
31 - 28
27 - 24
23 - 20
19 - 16
15 - 12
11 - 8
7 - 4
3 - 0
Byte Location
Phase
[7]
Phase
[6]
Phase
[5]
Phase
[4]
Phase
[3]
Phase
[2]
Phase
[1]
Phase
[0]
00h
Phase
[15]
Phase
[14]
Phase
[13]
Phase
[12]
Phase
[11]
Phase
[10]
Phase
[9]
Phase
[8]
04h
Phase
[23]
Phase
[22]
Phase
[21]
Phase
[20]
Phase
[19]
Phase
[18]
Phase
[17]
Phase
[16]
08h
Phase
[31]
Phase
[30]
Phase
[29]
Phase
[28]
Phase
[27]
Phase
[26]
Phase
[25]
Phase
[24]
0Ch
7.2.98
PORT ARBITRATION TABLE REGISTER (0) and (1) – OFFSET 180h and
1C0h
The Port arbitration table is a read-write register array that contains a table for Port arbitration. Each
table entry allocates two bits to represent Port Number. The table entry size is dependent on the
number of enabled ports (refer to bit 10 and 11 of Port VC capability register 1). The arbitration table
contains 128 entries if three or four ports are to be enabled. The following table shows the register
array layout for the size of entry equal to two.
Table 7-2 Table Entry Size in 4 Bits
63 - 56
55 - 48
47 - 40
39 - 32
31 - 24
23 - 16
15 - 8
7 - 0
Byte Location
Phase
[15:14]
Phase
[13:12]
Phase
[11:10]
Phase
[9:8]
Phase
[7:6]
Phase
[5:4]
Phase
[3:2]
Phase
[1:0]
00h
Phase
[31:30]
Phase
[29:28]
Phase
[27:26]
Phase
[25:24]
Phase
[23:22]
Phase
[21:20]
Phase
[19:18]
Phase
[17:16]
08h
Phase
[47:46]
Phase
[45:44]
Phase
[43:42]
Phase
[41:40]
Phase
[39:38]
Phase
[37:36]
Phase
[35:34]
Phase
[33:32]
10h
Phase
[63:62]
Phase
[61:60]
Phase
[59:58]
Phase
[57:56]
Phase
[55:54]
Phase
[53:52]
Phase
[51:50]
Phase
[49:48]
18h
Phase
[79:78]
Phase
[77:76]
Phase
[75:74]
Phase
[73:72]
Phase
[71:70]
Phase
[69:68]
Phase
[67:66]
Phase
[65:64]
20h
Phase
[95:94]
Phase
[93:92]
Phase
[91:90]
Phase
[89:88]
Phase
[87:86]
Phase
[85:84]
Phase
[83:82]
Phase
[81:80]
28h
Phase
[111:110]
Phase
[109:108]
Phase
[107:106]
Phase
[105:104]
Phase
[103:102]
Phase
[101:100]
Phase
[99:98]
Phase
[97:96]
30h
Phase
[127:126]
Phase
[125:124]
Phase
[123:122]
Phase
[121:120]
Phase
[119:118]
Phase
[117:116]
Phase
[115:114]
Phase
[113:112]
38h
7.2.99
PCI EXPRESS POWER BUDGETING CAPABILITY ID REGISTER –
OFFSET 20Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Extended
Capabilities ID
RO
Read as 0004h to indicate that these are PCI express extended capability
registers for power budgeting.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
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| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
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