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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 27 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
ADDRESS
PCI CFG
OFFSET
DESCRIPTION
36h
F4h (Port 3)
F4h: Bit [15:0]
Slot Capability 0 of Port 3
Bit [15:0]: Mapping to the low word of slot capability register
42h
F4h (Port 1)
F4h: Bit [31:16]
Slot Capability 1 of Port 1
Bit [15:0]: Mapping to the high word of slot capability register
44h
F4h (Port 2)
F4h: Bit [31:16]
Slot Capability 1 of Port 2
Bit [15:0]: Mapping to the high word of slot capability register
46h
F4h (Port 3)
F4h: Bit [31:16]
Slot Capability 1 of Port 3
Bit [15:0]: Mapping to the high word of slot capability register
50h
15Ch (Port 0)
15Ch– Bit [22:16]
160h– Bit [7:0]
VC1 MAX Time Slot and TC/VC Map for Port 0
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC is
mapped into VC1
52h
15Ch (Port 1)
15Ch– Bit [22:16]
160h– Bit [7:0]
VC1 MAX Time Slot and TC/VC Map for Port 1
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC is
mapped into VC1
54h
15Ch (Port 2)
15Ch– Bit [22:16]
160h– Bit [7:0]
VC1 MAX Time Slot and TC/VC Map for Port 2
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC is
mapped into
VC1
56h
15Ch (Port 3)
15Ch– Bit [22:16]
160h– Bit [7:0]
VC1 MAX Time Slot and TC/VC Map for Port 3
Bit [6:0]: The maximum time slot supported by VC1
Bit [15:8]: When set, it indicates the corresponding TC mapped
into VC1
60h
214h (Port 0)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 0
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
62h
214h (Port 1)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 1
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
64h
214h (Port 2)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 2
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
66h
214h (Port 3)
214h– Bit [7:0]
214h– Bit [9:8]
214h– Bit [14:13]
218h– Bit [0]
Power Budget Register for Port 3
Bit [7:0]: Base Power
Bit [9:8]: Data Scale
Bit [11:10]: PM State
Bit [15]: System Allocated
70h
B0h (Port 0)
B0h – Bit [15:0]
Replay Time-out Counter for Port 0
Bit [15:0]: Relay Time-out Counter
72h
B0h (Port 1)
B0h – Bit [15:0]
Replay Time-out Counter for Port 1
Bit [15:0]: Relay Time-out Counter
74h
B0h (Port 2)
B0h – Bit [15:0]
Replay Time-out Counter for Port 2
Bit [15:0]: Relay Time-out Counter
76h
B0h (Port 3)
B0h – Bit [15:0]
Replay Time-out Counter for Port 3
Bit [15:0]: Relay Time-out Counter
80h
B0h (Port 0)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 0
Bit [31:16]: Acknowledge Latency Timer
82h
B0h (Port 1)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 1
Bit [31:16]: Acknowledge Latency Timer
84h
B0h (Port 2)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 2
Bit [31:16]: Acknowledge Latency Timer
86h
B0h (Port 3)
B0h – Bit [31:16]
Acknowledge Latency Timer for Port 3
Bit [31:16]: Acknowledge Latency Timer
90h
B4h (Port 0)
B4h: Bit [31:16]
PHY Parameter for Port 0
Bit [31:16]: PHY Parameter