TM Family Datasheet Page 21 of 79 June 2009 – " />
參數(shù)資料
型號： PI7C9X20404GPBNBE
廠商： Pericom
文件頁數(shù)： 14/79頁
文件大小： 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 21 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
5.8
PORT ARBITRATION
Among multiple ingress ports, the port arbitration built in the egress port determines which input traffic to be
forwarded to the output port. The arbitration algorithm contains hardware fixed Round Robin, 128-phase Weighted
Round-Robin and programmable 128-phase time-based WRR. The port arbitration is held within the same VC
channel. It means that each port has two port arbitration circuitries for VC0 and VC1 respectively. At upstream port,
in addition to the traffic from inter-port, the intra-port packet such as configurations completion would also join the
arbitration loop to get the service in Virtual Channel 0.
5.9
VC ARBITRATION
After port arbitration, VC arbitration is executed among different VC channels within the same source. Three
arbitration algorithms are provided to choose the appropriate VC. They are respectively Strict Priority, Round Robin
or Weighted Round Robin.
5.10 FLOW CONTROL
PCI Express employs Credit-Based Flow Control mechanism to make buffer utilization more efficient. The
transaction layer transmitter ensures that it does not transmit a TLP to an opposite receiver unless the receiver has
enough buffer space to accept the TLP. The transaction layer receiver has the responsibility to advertise the free
buffer space to an opposite transmitter to avoid packet stale. In this switch, each port has separate queues for
different traffic types and the credits are on the fly sent to data link layer, which compares the current available
credits with the monitored one and reports the updated credit to the counterpart. If no new credit is acquired, the
credit reported is scheduled for every 30 us to prevent from link entering retrain. On the other hand, the receiver at
each egress port gets the usable credits from the opposite end in a link. It would broadcast them to all the other
ingress ports for gating the packet transmission.
5.11 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION)
The transmit portion of transaction layer performs the following functions. They are to construct the all types of
forwarded TLP generated from VC arbiter, respond with the completion packet when the local resource (i.e.
configuration register) is accessed and regenerate the message that terminated at receiver to RC if acts as an
upstream port.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCFDEX 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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PI7C9X20508GPANDE 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube
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