TM Family Datasheet Page 37 of 79 June 2009 – " />
參數(shù)資料
型號(hào)： PI7C9X20404GPBNBE
廠商： Pericom
文件頁(yè)數(shù)： 31/79頁(yè)
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開(kāi)關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤(pán)
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 37 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
31:20
Prefetchable Memory
Limit Address
[31:20]
RW
Defines the top address of an address range for the Bridge to determine when
to forward memory read and write transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits are assumed to be FFFFFh. The memory limit upper 32 bits
register contains the upper half of the limit address.
Reset to 000h.
7.2.21
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER
– OFFSET 28h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Prefetchable Memory
Base Address, Upper
32-bits [63:32]
RW
Defines the upper 32-bits of a 64-bit bottom address of an address range for
the Bridge to determine when to forward memory read and write transactions
from one interface to the other.
Reset to 00000000h.
7.2.22
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER
– OFFSET 2Ch
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Prefetchable Memory
Limit Address,
Upper 32-bits
[63:32]
RW
Defines the upper 32-bits of a 64-bit top address of an address range for the
Bridge to determine when to forward memory read and write transactions
from one interface to the other.
Reset to 00000000h.
7.2.23
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
I/O Base Address,
Upper 16-bits
[31:16]
RW
Defines the upper 16-bits of a 32-bit bottom address of an address range for
the Bridge to determine when to forward I/O transactions from one interface
to the other.
Reset to 0000h.
7.2.24
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
I/O Limit Address,
Upper 16-bits
[31:16]
RW
Defines the upper 16-bits of a 32-bit top address of an address range for the
Bridge to determine when to forward I/O transactions from one interface to
the other.
Reset to 0000h.
7.2.25
CAPABILITY POINTER REGISTER – OFFSET 34h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Capability Pointer
RO
Pointer points to the PCI power management registers (80h).
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