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| 型號(hào)： | PI7C9X20404GPBNBE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 4/79頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 148LFBGA |
| 產(chǎn)品變化通告： | Product Discontinuation Notice 22/Jan/2010 |
| 標(biāo)準(zhǔn)包裝： | 189 |
| 系列： | GreenPacket™ |
| 應(yīng)用： | 封裝開關(guān)，4 端口/4 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 148-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 148-LFBGA（12x12） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 12 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
3 PIN DESCRIPTION
3.1
PCI EXPRESS INTERFACE SIGNALS
NAME
PIN
TYPE
DESCRIPTION
REFCLKP
REFCLKN
A8
B8
I
Reference Clock Input Pairs: Connect to external 100MHz
differential clock.
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled interface so that only the AC information of
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in the AC-coupling.
PERP [3:0]
G14, L14,
N12, E12
I
PERN [3:0]
H14, K14,
P12, D12
I
PCI Express Data Serial Input Pairs: Differential data receive
signals in four ports.
Port 0 (Upstream Port) is PERP[0] and PERN[0]
Port 1 (Downstream Port) is PERP[1] and PERN[1]
Port 2 (Downstream Port) is PERP[2] and PERN[2]
Port 3 (Downstream Port) is PERP[3] and PERN[3]
PETP [3:0]
H12, K12,
P14, D14
O
PETN [3:0]
G12, L12,
N14, E14
O
PCI Express Data Serial Output Pairs: Differential data transmit
signals in four ports.
Port 0 (Upstream Port) is PETP[0] and PETN[0]
Port 1 (Downstream Port) is PETP[1] and PETN[1]
Port 2 (Downstream Port) is PETP[2] and PETN[2]
Port 3 (Downstream Port) is PETP[3] and PETN[3]
WAKEUP_L
A1
I
Wakeup Signal (Active LOW): When WAKEUP_L is asserted, the
upstream port has to generate a Beacon that is propagated to the Root
Complex/Power Management Controller. Pin has an internal pull-up.
RESET_L
D2
I
System Reset (Active LOW): When RESET_L is asserted, the
internal states of whole chip except sticky logics are initialized.
DWNRST_L [3:1]
B3, A3, C2
O
Downstream Device Reset (Active LOW): It provides a reset signal
to the devices connected to the downstream ports of Switch. The signal
is active when either RESET_L is asserted or the device is just plugged
into the Switch. DWNRST_L [x] corresponds to Portx, where x= 1,2,3.
3.2
PORT CONFIGURATION SIGNALS
NAME
PIN
TYPE
DESCRIPTION
VC1_EN
B1
I
Virtual Channel 1 Enable: The chip provides the capability to support
virtual channel 1 (VC1), in addition to the standard virtual channel 0.
When this pin is asserted high, Virtual Channel 1 is enabled, and
virtual channel resource sharing is not available. When it is asserted
low, the chip would allocate the additional VC1 resource to VC0, and
VC1 capability is disabled. The pin has internal pull-down.
SLOT_IMP [3:1]
B4, C4, E3
I
Slot Implemented: It decides if the downstream port is connected to
slot. SLOT_IMP [x] is correspondent to Portx, where x= 1,2,3.When
SLOT_IMP [x] is high, the Portx is connected to slot. By default,
downstream Port1, Port2, and Port3 are implemented with slots. The
pins have internal pull-up.
HOTPLUG [3:1]
A5, B5, C5
I
Hot Plug Capability: It determines if the downstream port is able to
support hot plug capability. HOTPLUG [x] is correspondent to Portx,
where x=1,2,3. When HOTPLUG [x] is high, Portx supports hot plug
operation. By default, downstream Port1, Port2, and Port3 are equipped
with hot plug function. The pins have internal pull-up.
SLOTCLK
F3
I
Slot Clock Configuration: It determines if the all downstream
components uses the same physical reference clock that the platform
provides on the connector. When SLOTCLK is high, the platform
reference clock is employed. By default, all downstream ports use the
same physical reference clock provided by platform. The pins have
internal pull-up.
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