TM Family Datasheet Page 32 of 79 June 2009 – " />
參數(shù)資料
型號： PI7C9X20404GPBNBE
廠商： Pericom
文件頁數(shù)： 26/79頁
文件大小： 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 32 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
7.2.1
VENDOR ID REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Vendor ID
RO
Identifies Pericom as the vendor of this device. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 12D8h.
7.2.2
DEVICE ID REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Device ID
RO
Identifies this device as the PI7C9X20404GP. The default value may be
changed by SMBus or auto-loading from EEPROM.
Resets to 0404h.
7.2.3
COMMAND REGISTER – OFFSET 04h
BIT
FUNCTION
TYPE
DESCRIPTION
0
I/O Space Enable
RW
0b: Ignores I/O transactions on the primary interface
1b: Enables responses to I/O transactions on the primary interface
Resets to 0b.
1
Memory Space
Enable
RW
0b: Ignores memory transactions on the primary interface
1b: Enables responses to memory transactions on the primary interface
Reset to 0b.
2
Bus Master Enable
RW
0b: Does not initiate memory or I/O transactions on the upstream port and
handles as an Unsupported Request (UR) to memory and I/O transactions
on the downstream port. For Non-Posted Requests, a completion with UR
completion status must be returned
1b: Enables the Switch Port to forward memory and I/O Read/Write
transactions in the upstream direction
Reset to 0b.
3
Special Cycle Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
4
Memory Write And
Invalidate Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
5
VGA Palette Snoop
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
6
Parity Error
Response Enable
RW
0b: Switch may ignore any parity errors that it detects and continue normal
operation
1b: Switch must take its normal action when a parity error is detected
Reset to 0b.
7
Wait Cycle Control
RO
Does not apply to PCI Express. Must be hardwired to 0.
8
SERR# enable
RW
0b: Disables the reporting of Non-fatal and Fatal errors detected by the
Switch to the Root Complex
b1: Enables the Non-fatal and Fatal error reporting to Root Complex
Reset to 0b.
9
Fast Back-to-Back
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
10
Interrupt Disable
RW
Controls the ability of a PCI Express device to generate INTx Interrupt
Messages. In the Switch, this bit does not affect the forwarding of INTx
messages from the downstream ports.
Reset to 0b.
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