TM Family Datasheet Page 25 of 79 June 2009 – " />
參數(shù)資料
型號(hào)： PI7C9X20404GPBNBE
廠商： Pericom
文件頁數(shù)： 18/79頁
文件大?。?/td> 0K
描述： IC PCIE PACKET SWITCH 148LFBGA
產(chǎn)品變化通告： Product Discontinuation Notice 22/Jan/2010
標(biāo)準(zhǔn)包裝： 189
系列： GreenPacket™
應(yīng)用： 封裝開關(guān)，4 端口/4 線道
接口： PCI Express
封裝/外殼： 148-LFBGA
供應(yīng)商設(shè)備封裝： 148-LFBGA（12x12）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20404GP
4Port-4Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 25 of 79
June 2009 – Revision 1.6
Pericom Semiconductor
ADDRESS
PCI CFG
OFFSET
DESCRIPTION
A8h: Bit [14:13]
Bit [9:8]: It represents RefClk ppm difference between the two
ends in one link; 00: 0 ppm, 01: 100 ppm, 10: 200 ppm, 11: 300
ppm
10h
84h (Port 0)
84h: Bit [3]
80h (Port 0)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 0
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 0
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
11h
84h (Port 0)
84h: Bit [31:24]
Power Management Data for Port 0
Bit [15:8]: read only as Data register
12h
84h (Port 1)
84h: Bit [3]
80h (Port 1)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 1
Bit [0]: No_Soft_Reset.
Power Management Capability for Port 1
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
13h
84h (Port 1)
84h: Bit [31:24]
Power Management Data for Port 1
Bit [15:8] – read only as Data register
14h
84h (Port 2)
84h: Bit [3]
80h (Port 2)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 2
Bit [0]: No_Soft_Reset
Power Management Capability for Port 2
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
15h
84h (Port 2)
84h: Bit [31:24]
Power Management Data for Port 2
Bit [15:8] – read only as Data register
16h
84h (Port 3)
84h: Bit [3]
80h (Port 3)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
No_Soft_Reset for Port 3
Bit [0]: No_Soft_Reset
Power Management Capability for Port 3
Bit [3:1]: AUX Current
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
17h
84h (Port 3)
84h: Bit [31:24]
Power Management Data for Port 3
Bit [15:8] – read only as Data register
20h
F0h (Port 0)
F0h: Bit [28]
80h (Port 0)
80h: Bit[21]
144h (Port 0)
144h: Bit [4]
ECh (Port 0)
ECh: Bit [25:24]
Slot Clock Configuration for Port 0
Bit [1]: When set, the component uses the clock provided on the
connector
Device specific Initialization for Port 0
Bit [2]: When set, the DSI is required
LPVC Count for Port 0
Bit [3]: When set, the VC1 is allocated to LPVC of Egress Port 0
Port Number for Port 0
Bit [5:4]: It represents the logic port numbering for physical port
0
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參數(shù)描述
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