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Modes of Operation
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
47
2.4.4
External Output Clock
The CC provides a continuous external output clock signal on the CLKOUT pin; this signal can be either
disabled or set to a frequency of 4, 10, or 40 MHz. The signal is always active after the power-up of the
CC, in all CC states including the hard reset state. The CLKOUT signal is disabled during the internal
power-on and low voltage reset procedures (refer to
Chapter 5, “Clocks and Reset Generator
”,
Section A.2.2, “Chip Power-up and Voltage Drops
”, and the figures below (
Figure 2-6
,
Figure 2-7
, and
Figure 2-8
) for more information). The CLK_S[1:0] input pins enable/disable the CLKOUT signal and
select its output frequency in accordance with the
Table 2-2
.
Figure 2-6
and
Figure 2-7
depict the CLKOUT generation during external hard reset and internal resets.
Refer to
Chapter 5, “Clocks and Reset Generator
for more information.
Figure 2-6. CLKOUT Generation During Power-on Reset
POR1
VDD
OSC clk output
Internal startup counter3
Internal CLK_S[1:0] latches3
CLKOUT divider internal reset3,
the divider is based on a counter
CLKOUT divider/counter output
~16000 μT
Latching window
Counter starts counting
Counter maximum value
Counter is reset
Counter does not count
Max. count value defined by
CLK_S[1:0] latched values
Where:
~16000
0
CLKOUT output
t
UPOSC2
Notes:
1
For more information on the POR, refer to
A.2.2, “Chip Power-up and Voltage Drops
”.
2
For more information on the t
UPOSC
, refer to
A.3, “Reset and Oscillator
”.
3
For more information on the Internal Startup Counter, the Internal CLK_S[1:0] latches, and the CLKOUT
divider internal reset signals, refer to
Chapter 5, “Clocks and Reset Generator
.