![](http://datasheet.mmic.net.cn/370000/PFR4200MAE40_datasheet_16728610/PFR4200MAE40_252.png)
MFR4200 Protocol Implementation Document
MFR4200 Data Sheet, Rev. 0
252
Freescale Semiconductor
Moreover, in Figure 7-6 (PS V1.1), and in similar drawings for nodes B and C, the state
Initialize schedule
lasts until the end of the communication cycle, rather than changing in the middle of the cycle.
C.8
Clock Synchronization
C.8.1
Introduction
The implementation is compliant with PS V1.1.
C.8.2
Time Representation
The implementation is compliant with PS V1.1.
C.8.3
Synchronization Process
Figure 8-3 (PS V1.1): In MFR4200 the measurement tables are initialized during the NIT (before cycle
start, rather than after the cycle start). The entries for the even cycle are initialized in the NIT of the odd
cycle. Likewise, the measurements of the odd cycle are initialized in the NIT of the even cycle.
C.8.4
Clock Startup
The implementation is compliant with PS V1.1.
C.8.5
Time Measurement
The implementation is compliant with PS V1.1. However, note that the clock sync measurement values
indicated in the host interface are different from the example shown in Figure 8-8 (PS V1.1).
C.8.5.1
Data Structure
The implementation is compliant with PS V1.1.
C.8.5.2
Initialization
In MFR4200, the table for the odd cycle measurements is initialized in the NIT of the even cycle, and vice
versa, rather than after the beginning of the even cycle.
C.8.6
Correction Term Calculation
Figure 8-13 (PS V1.1): MFR4200 differs slightly from this description. Startup frames are counted on a
per channel basis, with one counter for each channel, rather than one counter for both channels. For
evaluation, the maximum is taken, rather than counting a startup frame on either channel with a single
counter. Moreover, in MFR4200, the check of
vOffsetCorrection
is performed before the external offset
correction, rather than after external offset correction.